Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9831 |
1 |
|
T14 |
1 |
|
T10 |
1 |
|
T15 |
2 |
| others[1] |
482 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T24 |
19 |
| others[2] |
451 |
1 |
|
T24 |
12 |
|
T19 |
6 |
|
T47 |
1 |
| others[3] |
791 |
1 |
|
T2 |
1 |
|
T24 |
16 |
|
T21 |
2 |
| false |
233 |
1 |
|
T24 |
3 |
|
T21 |
1 |
|
T19 |
2 |
| true |
2305 |
1 |
|
T1 |
1 |
|
T55 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9639 |
1 |
|
T24 |
7 |
|
T26 |
100 |
|
T56 |
100 |
| others[1] |
268 |
1 |
|
T24 |
11 |
|
T73 |
1 |
|
T51 |
1 |
| others[2] |
254 |
1 |
|
T24 |
4 |
|
T5 |
1 |
|
T22 |
12 |
| others[3] |
480 |
1 |
|
T24 |
16 |
|
T30 |
1 |
|
T37 |
1 |
| false |
144 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
6 |
| true |
3308 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9627 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
10 |
| others[1] |
258 |
1 |
|
T24 |
10 |
|
T6 |
1 |
|
T110 |
1 |
| others[2] |
220 |
1 |
|
T15 |
1 |
|
T24 |
6 |
|
T57 |
1 |
| others[3] |
412 |
1 |
|
T24 |
19 |
|
T37 |
2 |
|
T22 |
22 |
| false |
147 |
1 |
|
T24 |
6 |
|
T51 |
1 |
|
T22 |
5 |
| true |
3429 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10186 |
1 |
|
T24 |
25 |
|
T26 |
100 |
|
T21 |
3 |
| others[1] |
835 |
1 |
|
T14 |
1 |
|
T24 |
22 |
|
T21 |
4 |
| others[2] |
846 |
1 |
|
T15 |
1 |
|
T24 |
22 |
|
T113 |
1 |
| others[3] |
1362 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
26 |
| false |
382 |
1 |
|
T10 |
1 |
|
T24 |
6 |
|
T19 |
5 |
| true |
482 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10165 |
1 |
|
T24 |
17 |
|
T26 |
100 |
|
T21 |
4 |
| others[1] |
855 |
1 |
|
T15 |
1 |
|
T24 |
21 |
|
T113 |
1 |
| others[2] |
814 |
1 |
|
T18 |
1 |
|
T24 |
18 |
|
T30 |
1 |
| others[3] |
1327 |
1 |
|
T24 |
34 |
|
T21 |
5 |
|
T19 |
21 |
| false |
431 |
1 |
|
T24 |
11 |
|
T21 |
4 |
|
T19 |
9 |
| true |
501 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2409 |
1 |
|
T18 |
1 |
|
T24 |
5 |
|
T26 |
22 |
| others[1] |
2459 |
1 |
|
T15 |
1 |
|
T24 |
15 |
|
T26 |
26 |
| others[2] |
2400 |
1 |
|
T24 |
13 |
|
T26 |
17 |
|
T56 |
17 |
| others[3] |
3991 |
1 |
|
T24 |
14 |
|
T26 |
26 |
|
T56 |
34 |
| false |
1274 |
1 |
|
T15 |
1 |
|
T24 |
7 |
|
T113 |
1 |
| true |
1560 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9641 |
1 |
|
T14 |
1 |
|
T4 |
1 |
|
T24 |
11 |
| others[1] |
288 |
1 |
|
T3 |
1 |
|
T24 |
8 |
|
T37 |
1 |
| others[2] |
260 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
5 |
| others[3] |
470 |
1 |
|
T24 |
18 |
|
T110 |
1 |
|
T164 |
1 |
| false |
129 |
1 |
|
T24 |
2 |
|
T27 |
1 |
|
T22 |
4 |
| true |
3305 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9836 |
1 |
|
T15 |
1 |
|
T24 |
15 |
|
T26 |
100 |
| others[1] |
484 |
1 |
|
T24 |
8 |
|
T113 |
1 |
|
T21 |
1 |
| others[2] |
428 |
1 |
|
T15 |
1 |
|
T24 |
8 |
|
T21 |
3 |
| others[3] |
796 |
1 |
|
T4 |
1 |
|
T24 |
15 |
|
T21 |
2 |
| false |
269 |
1 |
|
T24 |
4 |
|
T21 |
1 |
|
T6 |
1 |
| true |
2280 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9640 |
1 |
|
T14 |
1 |
|
T24 |
11 |
|
T26 |
100 |
| others[1] |
267 |
1 |
|
T24 |
10 |
|
T5 |
1 |
|
T57 |
1 |
| others[2] |
273 |
1 |
|
T24 |
11 |
|
T37 |
1 |
|
T47 |
1 |
| others[3] |
471 |
1 |
|
T24 |
18 |
|
T30 |
1 |
|
T51 |
1 |
| false |
136 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
3 |
| true |
3306 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9618 |
1 |
|
T15 |
1 |
|
T24 |
6 |
|
T26 |
100 |
| others[1] |
249 |
1 |
|
T15 |
1 |
|
T24 |
8 |
|
T57 |
1 |
| others[2] |
262 |
1 |
|
T55 |
1 |
|
T24 |
10 |
|
T164 |
1 |
| others[3] |
426 |
1 |
|
T24 |
16 |
|
T37 |
1 |
|
T34 |
1 |
| false |
125 |
1 |
|
T24 |
2 |
|
T22 |
4 |
|
T75 |
2 |
| true |
3413 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10167 |
1 |
|
T3 |
1 |
|
T24 |
18 |
|
T26 |
100 |
| others[1] |
836 |
1 |
|
T15 |
1 |
|
T24 |
19 |
|
T21 |
2 |
| others[2] |
821 |
1 |
|
T18 |
1 |
|
T24 |
23 |
|
T21 |
4 |
| others[3] |
1316 |
1 |
|
T10 |
1 |
|
T24 |
35 |
|
T113 |
1 |
| false |
452 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
6 |
| true |
501 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10179 |
1 |
|
T18 |
1 |
|
T24 |
19 |
|
T26 |
100 |
| others[1] |
829 |
1 |
|
T24 |
21 |
|
T21 |
2 |
|
T19 |
6 |
| others[2] |
788 |
1 |
|
T15 |
1 |
|
T24 |
22 |
|
T21 |
2 |
| others[3] |
1347 |
1 |
|
T24 |
30 |
|
T21 |
8 |
|
T57 |
1 |
| false |
413 |
1 |
|
T15 |
1 |
|
T24 |
9 |
|
T113 |
1 |
| true |
537 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2370 |
1 |
|
T18 |
1 |
|
T24 |
11 |
|
T113 |
1 |
| others[1] |
2451 |
1 |
|
T24 |
9 |
|
T26 |
20 |
|
T56 |
25 |
| others[2] |
2483 |
1 |
|
T15 |
2 |
|
T24 |
12 |
|
T26 |
21 |
| others[3] |
4012 |
1 |
|
T55 |
1 |
|
T24 |
23 |
|
T26 |
31 |
| false |
1190 |
1 |
|
T24 |
5 |
|
T26 |
7 |
|
T56 |
7 |
| true |
1587 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9657 |
1 |
|
T24 |
11 |
|
T26 |
100 |
|
T5 |
1 |
| others[1] |
275 |
1 |
|
T24 |
8 |
|
T189 |
1 |
|
T22 |
19 |
| others[2] |
290 |
1 |
|
T18 |
1 |
|
T24 |
6 |
|
T113 |
1 |
| others[3] |
486 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
137 |
1 |
|
T24 |
8 |
|
T28 |
1 |
|
T22 |
3 |
| true |
3248 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9795 |
1 |
|
T24 |
6 |
|
T26 |
100 |
|
T21 |
1 |
| others[1] |
464 |
1 |
|
T1 |
1 |
|
T55 |
1 |
|
T24 |
11 |
| others[2] |
482 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T24 |
15 |
| others[3] |
780 |
1 |
|
T24 |
21 |
|
T21 |
3 |
|
T19 |
8 |
| false |
241 |
1 |
|
T15 |
1 |
|
T24 |
7 |
|
T21 |
1 |
| true |
2331 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9633 |
1 |
|
T24 |
7 |
|
T26 |
100 |
|
T6 |
1 |
| others[1] |
260 |
1 |
|
T15 |
1 |
|
T24 |
11 |
|
T47 |
1 |
| others[2] |
245 |
1 |
|
T24 |
14 |
|
T113 |
1 |
|
T5 |
1 |
| others[3] |
459 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T24 |
16 |
| false |
132 |
1 |
|
T24 |
6 |
|
T22 |
2 |
|
T75 |
3 |
| true |
3364 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9623 |
1 |
|
T24 |
9 |
|
T26 |
100 |
|
T56 |
100 |
| others[1] |
238 |
1 |
|
T15 |
1 |
|
T24 |
9 |
|
T37 |
1 |
| others[2] |
255 |
1 |
|
T15 |
1 |
|
T24 |
10 |
|
T189 |
1 |
| others[3] |
418 |
1 |
|
T24 |
19 |
|
T33 |
1 |
|
T110 |
1 |
| false |
122 |
1 |
|
T24 |
3 |
|
T164 |
1 |
|
T22 |
7 |
| true |
3437 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10177 |
1 |
|
T18 |
1 |
|
T24 |
24 |
|
T26 |
100 |
| others[1] |
823 |
1 |
|
T10 |
1 |
|
T24 |
15 |
|
T21 |
3 |
| others[2] |
808 |
1 |
|
T24 |
18 |
|
T21 |
5 |
|
T19 |
15 |
| others[3] |
1351 |
1 |
|
T24 |
34 |
|
T113 |
1 |
|
T21 |
1 |
| false |
439 |
1 |
|
T15 |
1 |
|
T24 |
10 |
|
T21 |
1 |
| true |
495 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10165 |
1 |
|
T24 |
18 |
|
T113 |
1 |
|
T26 |
100 |
| others[1] |
837 |
1 |
|
T24 |
16 |
|
T21 |
3 |
|
T30 |
1 |
| others[2] |
776 |
1 |
|
T18 |
1 |
|
T24 |
23 |
|
T21 |
2 |
| others[3] |
1347 |
1 |
|
T15 |
1 |
|
T24 |
31 |
|
T21 |
7 |
| false |
450 |
1 |
|
T14 |
1 |
|
T24 |
13 |
|
T21 |
1 |
| true |
518 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2422 |
1 |
|
T24 |
10 |
|
T26 |
20 |
|
T56 |
21 |
| others[1] |
2460 |
1 |
|
T15 |
1 |
|
T24 |
12 |
|
T26 |
20 |
| others[2] |
2440 |
1 |
|
T15 |
1 |
|
T24 |
6 |
|
T26 |
20 |
| others[3] |
3959 |
1 |
|
T24 |
15 |
|
T26 |
33 |
|
T56 |
33 |
| false |
1240 |
1 |
|
T18 |
1 |
|
T24 |
7 |
|
T113 |
1 |
| true |
1572 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9627 |
1 |
|
T24 |
10 |
|
T26 |
100 |
|
T30 |
1 |
| others[1] |
262 |
1 |
|
T15 |
1 |
|
T24 |
12 |
|
T73 |
1 |
| others[2] |
281 |
1 |
|
T24 |
12 |
|
T113 |
1 |
|
T164 |
1 |
| others[3] |
436 |
1 |
|
T55 |
1 |
|
T24 |
15 |
|
T22 |
16 |
| false |
153 |
1 |
|
T3 |
1 |
|
T24 |
3 |
|
T47 |
1 |
| true |
3334 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9861 |
1 |
|
T15 |
1 |
|
T24 |
9 |
|
T26 |
100 |
| others[1] |
492 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[2] |
473 |
1 |
|
T24 |
11 |
|
T19 |
4 |
|
T37 |
1 |
| others[3] |
763 |
1 |
|
T10 |
1 |
|
T55 |
1 |
|
T24 |
16 |
| false |
243 |
1 |
|
T18 |
1 |
|
T4 |
1 |
|
T24 |
6 |
| true |
2261 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9648 |
1 |
|
T24 |
8 |
|
T113 |
1 |
|
T26 |
100 |
| others[1] |
264 |
1 |
|
T24 |
5 |
|
T6 |
1 |
|
T22 |
4 |
| others[2] |
268 |
1 |
|
T3 |
1 |
|
T24 |
19 |
|
T110 |
1 |
| others[3] |
441 |
1 |
|
T15 |
1 |
|
T24 |
23 |
|
T30 |
1 |
| false |
122 |
1 |
|
T18 |
1 |
|
T24 |
5 |
|
T22 |
4 |
| true |
3350 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9627 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
16 |
| others[1] |
249 |
1 |
|
T24 |
6 |
|
T113 |
1 |
|
T22 |
7 |
| others[2] |
258 |
1 |
|
T55 |
1 |
|
T24 |
9 |
|
T22 |
20 |
| others[3] |
428 |
1 |
|
T15 |
1 |
|
T24 |
14 |
|
T22 |
14 |
| false |
142 |
1 |
|
T24 |
7 |
|
T73 |
1 |
|
T189 |
1 |
| true |
3389 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10150 |
1 |
|
T24 |
21 |
|
T26 |
100 |
|
T21 |
4 |
| others[1] |
816 |
1 |
|
T3 |
1 |
|
T24 |
20 |
|
T21 |
6 |
| others[2] |
801 |
1 |
|
T18 |
1 |
|
T24 |
21 |
|
T21 |
2 |
| others[3] |
1379 |
1 |
|
T15 |
1 |
|
T24 |
23 |
|
T21 |
3 |
| false |
445 |
1 |
|
T24 |
16 |
|
T113 |
1 |
|
T19 |
5 |
| true |
502 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |