Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	227179	1		T1	1		T2	2		T3	27
auto[FlashEraseBank]	253426	1		T2	10		T3	40		T14	16

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	266777	1		T2	11		T3	32		T14	41
auto[FlashOpProgram]	194157	1		T1	1		T2	1		T3	35
auto[FlashOpErase]	15671	1		T14	30		T24	55		T26	100
auto[FlashOpInvalid]	4000	1		T26	200		T56	200		T118	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	266777	1		T2	11		T3	32		T14	41
op[FlashOpProgram]	194157	1		T1	1		T2	1		T3	35
op[FlashOpErase]	15671	1		T14	30		T24	55		T26	100
read_erase_read	808	1		T14	24		T24	4		T31	1
read_prog_read	1318	1		T2	1		T3	17		T24	2

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	340754	1		T1	1		T2	5		T3	33
auto[FlashPartInfo]	135551	1		T2	5		T3	34		T14	48
auto[FlashPartInfo1]	992	1		T10	1		T4	16		T6	1
auto[FlashPartInfo2]	3308	1		T2	2		T14	1		T55	20

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	202753	1		T2	4		T3	11		T14	11
auto[FlashPartData]	auto[FlashOpProgram]	130353	1		T1	1		T2	1		T3	22
auto[FlashPartData]	auto[FlashOpErase]	3722	1		T14	11		T24	34		T26	98
auto[FlashPartData]	auto[FlashOpInvalid]	3926	1		T26	196		T56	196		T118	196
auto[FlashPartInfo]	auto[FlashOpRead]	61089	1		T2	5		T3	21		T14	29
auto[FlashPartInfo]	auto[FlashOpProgram]	62482	1		T3	13		T18	244		T24	546
auto[FlashPartInfo]	auto[FlashOpErase]	11914	1		T14	19		T24	20		T26	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	66	1		T26	4		T56	4		T118	2
auto[FlashPartInfo1]	auto[FlashOpRead]	819	1		T4	16		T6	1		T57	5
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T10	1		T87	32		T101	32
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T22	1		T118	1		T120	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T118	2		T120	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2116	1		T2	2		T14	1		T55	20
auto[FlashPartInfo2]	auto[FlashOpProgram]	1159	1		T6	4		T57	9		T88	1
auto[FlashPartInfo2]	auto[FlashOpErase]	29	1		T24	1		T390	1		T124	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T124	2		T391	2		-	-