Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30247	1		T3	21		T24	8		T26	400
auto[1]	126	1		T27	2		T161	6		T321	3
auto[2]	40	1		T25	20		T197	3		T195	4
auto[3]	247	1		T36	2		T193	1		T116	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7696	1		T3	3		T24	2		T26	100
evic_idx[1]	7682	1		T3	7		T24	2		T26	100
evic_idx[2]	7644	1		T3	6		T24	2		T26	100
evic_idx[3]	7638	1		T3	5		T24	2		T26	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29562	1		T26	400		T56	400		T40	592
evic_op[2]	432	1		T3	21		T24	8		T57	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[1]]	[auto[2]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7313	1		T26	100		T56	100		T40	148
evic_idx[0]	evic_op[1]	auto[1]	34	1		T322	12		T323	22		-	-
evic_idx[0]	evic_op[1]	auto[3]	70	1		T191	22		T324	15		T325	33
evic_idx[0]	evic_op[2]	auto[0]	87	1		T3	3		T24	2		T57	1
evic_idx[0]	evic_op[2]	auto[1]	6	1		T27	1		T161	2		T326	1
evic_idx[0]	evic_op[2]	auto[2]	6	1		T197	1		T195	1		T327	2
evic_idx[0]	evic_op[2]	auto[3]	13	1		T36	1		T193	1		T194	1
evic_idx[1]	evic_op[1]	auto[0]	7314	1		T26	100		T56	100		T40	148
evic_idx[1]	evic_op[1]	auto[1]	31	1		T322	9		T323	22		-	-
evic_idx[1]	evic_op[1]	auto[3]	55	1		T191	18		T324	14		T325	23
evic_idx[1]	evic_op[2]	auto[0]	92	1		T3	7		T24	2		T328	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T161	2		T329	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	2	1		T197	1		T195	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	18	1		T36	1		T116	1		T330	1
evic_idx[2]	evic_op[1]	auto[0]	7314	1		T26	100		T56	100		T40	148
evic_idx[2]	evic_op[1]	auto[1]	23	1		T322	7		T323	16		-	-
evic_idx[2]	evic_op[1]	auto[3]	36	1		T191	14		T324	7		T325	15
evic_idx[2]	evic_op[2]	auto[0]	87	1		T3	6		T24	2		T57	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T161	1		T321	1		T331	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T195	1		T332	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	13	1		T333	1		T334	1		T335	1
evic_idx[3]	evic_op[1]	auto[0]	7313	1		T26	100		T56	100		T40	148
evic_idx[3]	evic_op[1]	auto[1]	22	1		T322	8		T323	14		-	-
evic_idx[3]	evic_op[1]	auto[2]	2	1		T255	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	35	1		T191	12		T324	8		T325	15
evic_idx[3]	evic_op[2]	auto[0]	85	1		T3	5		T24	2		T84	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T27	1		T161	1		T321	2
evic_idx[3]	evic_op[2]	auto[2]	4	1		T197	1		T195	1		T332	2
evic_idx[3]	evic_op[2]	auto[3]	7	1		T333	1		T336	1		T337	1