Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	13410	1		T304	2603		T305	8175		T306	2632
rd_lvl[2]	34024	1		T307	6920		T304	1694		T305	3937
rd_lvl[3]	14044	1		T73	2756		T308	858		T309	1226
rd_lvl[4]	33955	1		T73	1629		T310	2146		T311	2026
rd_lvl[5]	29027	1		T4	1743		T310	1046		T311	1280
rd_lvl[6]	11053	1		T4	451		T311	84		T312	970
rd_lvl[7]	11288	1		T74	1153		T313	1132		T311	102
rd_lvl[8]	10192	1		T4	10		T74	689		T313	690
rd_lvl[9]	5216	1		T32	596		T74	1		T314	131
rd_lvl[10]	6213	1		T5	711		T32	505		T74	1
rd_lvl[11]	7119	1		T4	10		T5	531		T30	296
rd_lvl[12]	8565	1		T30	886		T32	24		T315	316
rd_lvl[13]	6566	1		T5	29		T254	701		T308	42
rd_lvl[14]	3690	1		T30	6		T254	452		T316	478
rd_lvl[15]	2550	1		T316	298		T260	458		T317	32