Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	296376	1		T1	2		T2	1		T3	1
all_pins[1]	296376	1		T1	2		T2	1		T3	1
all_pins[2]	296376	1		T1	2		T2	1		T3	1
all_pins[3]	296376	1		T1	2		T2	1		T3	1
all_pins[4]	296376	1		T1	2		T2	1		T3	1
all_pins[5]	296376	1		T1	2		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1473900	1		T1	12		T2	6		T3	6
values[0x1]	304356	1		T18	1320		T4	3262		T5	2542
transitions[0x0=>0x1]	278401	1		T18	1320		T4	3188		T5	2542
transitions[0x1=>0x0]	278382	1		T18	1320		T4	3188		T5	2542

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	296221	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	155	1		T248	1		T249	7		T250	6
all_pins[0]	transitions[0x0=>0x1]	77	1		T249	5		T250	4		T300	1
all_pins[0]	transitions[0x1=>0x0]	78	1		T248	1		T249	1		T250	1
all_pins[1]	values[0x0]	296220	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	156	1		T248	2		T249	3		T250	3
all_pins[1]	transitions[0x0=>0x1]	126	1		T248	1		T249	3		T250	3
all_pins[1]	transitions[0x1=>0x0]	1870	1		T260	450		T338	589		T339	369
all_pins[2]	values[0x0]	294476	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	1900	1		T260	450		T338	589		T339	369
all_pins[2]	transitions[0x0=>0x1]	48	1		T248	1		T300	1		T299	1
all_pins[2]	transitions[0x1=>0x0]	197957	1		T4	2214		T5	1271		T30	1188
all_pins[3]	values[0x0]	96567	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	199809	1		T4	2214		T5	1271		T30	1188
all_pins[3]	transitions[0x0=>0x1]	175865	1		T4	2140		T5	1271		T30	1188
all_pins[3]	transitions[0x1=>0x0]	78335	1		T18	1320		T4	974		T5	1271
all_pins[4]	values[0x0]	194097	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	102279	1		T18	1320		T4	1048		T5	1271
all_pins[4]	transitions[0x0=>0x1]	102264	1		T18	1320		T4	1048		T5	1271
all_pins[4]	transitions[0x1=>0x0]	42	1		T249	3		T250	1		T299	2
all_pins[5]	values[0x0]	296319	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	57	1		T248	2		T249	5		T250	1
all_pins[5]	transitions[0x0=>0x1]	21	1		T248	1		T299	2		T303	2
all_pins[5]	transitions[0x1=>0x0]	100	1		T249	2		T250	4		T300	2