Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T248	4		T249	7		T250	7
all_values[1]	269	1		T248	4		T249	7		T250	7
all_values[2]	269	1		T248	4		T249	7		T250	7
all_values[3]	269	1		T248	4		T249	7		T250	7
all_values[4]	269	1		T248	4		T249	7		T250	7
all_values[5]	269	1		T248	4		T249	7		T250	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	897	1		T248	14		T249	18		T250	22
auto[1]	717	1		T248	10		T249	24		T250	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	551	1		T248	7		T249	12		T250	17
auto[1]	1063	1		T248	17		T249	30		T250	25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	948	1		T248	16		T249	25		T250	26
auto[1]	666	1		T248	8		T249	17		T250	16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	78	1		T248	3		T250	1		T299	4
all_values[0]	auto[0]	auto[1]	auto[1]	71	1		T249	3		T250	5		T300	2
all_values[0]	auto[1]	auto[0]	auto[1]	73	1		T248	1		T250	1		T300	2
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T249	4		T299	1		T301	3
all_values[1]	auto[0]	auto[0]	auto[1]	79	1		T248	2		T249	2		T250	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1		T248	1		T249	4		T300	1
all_values[1]	auto[1]	auto[0]	auto[1]	55	1		T249	1		T250	2		T300	2
all_values[1]	auto[1]	auto[1]	auto[1]	55	1		T248	1		T250	4		T299	2
all_values[2]	auto[0]	auto[0]	auto[0]	80	1		T248	1		T249	1		T250	4
all_values[2]	auto[0]	auto[1]	auto[0]	79	1		T248	1		T249	4		T250	3
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T248	1		T249	2		T299	1
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T248	1		T300	1		T299	2
all_values[3]	auto[0]	auto[0]	auto[0]	98	1		T248	2		T249	4		T250	1
all_values[3]	auto[0]	auto[1]	auto[0]	63	1		T248	1		T250	2		T299	1
all_values[3]	auto[1]	auto[0]	auto[1]	68	1		T249	3		T250	1		T300	2
all_values[3]	auto[1]	auto[1]	auto[1]	40	1		T248	1		T250	3		T300	1
all_values[4]	auto[0]	auto[0]	auto[0]	73	1		T248	2		T249	2		T250	3
all_values[4]	auto[0]	auto[0]	auto[1]	13	1		T300	1		T299	1		T302	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T249	1		T250	1		T300	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T248	1		T249	1		T250	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T249	1		T250	2		T300	2
all_values[4]	auto[1]	auto[1]	auto[1]	53	1		T248	1		T249	2		T299	3
all_values[5]	auto[0]	auto[0]	auto[0]	71	1		T250	3		T300	2		T299	3
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T249	1		T250	1		T299	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1		T300	2		T301	2		T303	3
all_values[5]	auto[0]	auto[1]	auto[1]	22	1		T248	2		T249	2		T299	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T248	2		T249	1		T250	2
all_values[5]	auto[1]	auto[1]	auto[1]	39	1		T249	3		T250	1		T301	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal