| T1079 |
/workspace/coverage/default/15.flash_ctrl_wo.1512166846 |
|
|
Apr 02 03:27:26 PM PDT 24 |
Apr 02 03:29:34 PM PDT 24 |
6763652800 ps |
| T1080 |
/workspace/coverage/default/48.flash_ctrl_alert_test.199085578 |
|
|
Apr 02 03:31:03 PM PDT 24 |
Apr 02 03:31:16 PM PDT 24 |
28677400 ps |
| T1081 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.173637394 |
|
|
Apr 02 03:24:31 PM PDT 24 |
Apr 02 03:24:53 PM PDT 24 |
92201900 ps |
| T1082 |
/workspace/coverage/default/5.flash_ctrl_sec_info_access.3226627351 |
|
|
Apr 02 03:25:07 PM PDT 24 |
Apr 02 03:26:13 PM PDT 24 |
1831733900 ps |
| T213 |
/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.466883721 |
|
|
Apr 02 03:24:00 PM PDT 24 |
Apr 02 03:24:22 PM PDT 24 |
364124300 ps |
| T1083 |
/workspace/coverage/default/55.flash_ctrl_otp_reset.895543457 |
|
|
Apr 02 03:31:11 PM PDT 24 |
Apr 02 03:33:26 PM PDT 24 |
154127600 ps |
| T1084 |
/workspace/coverage/default/39.flash_ctrl_disable.3300582038 |
|
|
Apr 02 03:30:30 PM PDT 24 |
Apr 02 03:30:52 PM PDT 24 |
15689900 ps |
| T1085 |
/workspace/coverage/default/36.flash_ctrl_connect.2280085233 |
|
|
Apr 02 03:30:17 PM PDT 24 |
Apr 02 03:30:33 PM PDT 24 |
85510900 ps |
| T1086 |
/workspace/coverage/default/2.flash_ctrl_alert_test.2684723732 |
|
|
Apr 02 03:24:26 PM PDT 24 |
Apr 02 03:24:43 PM PDT 24 |
114190000 ps |
| T1087 |
/workspace/coverage/default/66.flash_ctrl_connect.2502948431 |
|
|
Apr 02 03:31:29 PM PDT 24 |
Apr 02 03:31:42 PM PDT 24 |
148600300 ps |
| T363 |
/workspace/coverage/default/16.flash_ctrl_disable.80213327 |
|
|
Apr 02 03:27:40 PM PDT 24 |
Apr 02 03:28:01 PM PDT 24 |
20419200 ps |
| T1088 |
/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.633957778 |
|
|
Apr 02 03:28:24 PM PDT 24 |
Apr 02 03:28:38 PM PDT 24 |
171501800 ps |
| T1089 |
/workspace/coverage/default/10.flash_ctrl_rw_evict.2251231075 |
|
|
Apr 02 03:26:27 PM PDT 24 |
Apr 02 03:26:58 PM PDT 24 |
153587400 ps |
| T1090 |
/workspace/coverage/default/5.flash_ctrl_rand_ops.447272528 |
|
|
Apr 02 03:24:52 PM PDT 24 |
Apr 02 03:29:54 PM PDT 24 |
3026247400 ps |
| T1091 |
/workspace/coverage/default/39.flash_ctrl_smoke.988621631 |
|
|
Apr 02 03:30:27 PM PDT 24 |
Apr 02 03:33:44 PM PDT 24 |
355246800 ps |
| T1092 |
/workspace/coverage/default/49.flash_ctrl_otp_reset.517702422 |
|
|
Apr 02 03:31:06 PM PDT 24 |
Apr 02 03:33:17 PM PDT 24 |
77762700 ps |
| T1093 |
/workspace/coverage/default/2.flash_ctrl_oversize_error.2528361354 |
|
|
Apr 02 03:24:19 PM PDT 24 |
Apr 02 03:26:52 PM PDT 24 |
1344486300 ps |
| T1094 |
/workspace/coverage/default/21.flash_ctrl_connect.2777577504 |
|
|
Apr 02 03:28:41 PM PDT 24 |
Apr 02 03:28:57 PM PDT 24 |
14285400 ps |
| T1095 |
/workspace/coverage/default/1.flash_ctrl_connect.3251630906 |
|
|
Apr 02 03:24:10 PM PDT 24 |
Apr 02 03:24:25 PM PDT 24 |
25563200 ps |
| T1096 |
/workspace/coverage/default/13.flash_ctrl_ro.3097260923 |
|
|
Apr 02 03:26:55 PM PDT 24 |
Apr 02 03:28:54 PM PDT 24 |
483027900 ps |
| T1097 |
/workspace/coverage/default/65.flash_ctrl_connect.3591451574 |
|
|
Apr 02 03:31:23 PM PDT 24 |
Apr 02 03:31:40 PM PDT 24 |
16045300 ps |
| T1098 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.2984152074 |
|
|
Apr 02 03:27:20 PM PDT 24 |
Apr 02 03:33:40 PM PDT 24 |
1428799000 ps |
| T1099 |
/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2941394491 |
|
|
Apr 02 03:25:33 PM PDT 24 |
Apr 02 03:25:47 PM PDT 24 |
15035400 ps |
| T1100 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.744440857 |
|
|
Apr 02 03:26:40 PM PDT 24 |
Apr 02 03:26:53 PM PDT 24 |
47426100 ps |
| T1101 |
/workspace/coverage/default/14.flash_ctrl_phy_arb.2924611332 |
|
|
Apr 02 03:27:10 PM PDT 24 |
Apr 02 03:33:18 PM PDT 24 |
2075955200 ps |
| T1102 |
/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1402856215 |
|
|
Apr 02 03:28:10 PM PDT 24 |
Apr 02 03:28:24 PM PDT 24 |
15378500 ps |
| T1103 |
/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2481299197 |
|
|
Apr 02 03:27:22 PM PDT 24 |
Apr 02 03:29:08 PM PDT 24 |
2778401300 ps |
| T1104 |
/workspace/coverage/default/11.flash_ctrl_alert_test.1763838184 |
|
|
Apr 02 03:26:40 PM PDT 24 |
Apr 02 03:26:54 PM PDT 24 |
40052700 ps |
| T1105 |
/workspace/coverage/default/25.flash_ctrl_smoke.1374355933 |
|
|
Apr 02 03:29:05 PM PDT 24 |
Apr 02 03:30:20 PM PDT 24 |
35348200 ps |
| T331 |
/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.1008105214 |
|
|
Apr 02 03:27:14 PM PDT 24 |
Apr 02 03:27:45 PM PDT 24 |
174976400 ps |
| T69 |
/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.142539144 |
|
|
Apr 02 03:24:25 PM PDT 24 |
Apr 02 03:24:41 PM PDT 24 |
15819600 ps |
| T1106 |
/workspace/coverage/default/0.flash_ctrl_derr_detect.2076961469 |
|
|
Apr 02 03:24:03 PM PDT 24 |
Apr 02 03:25:49 PM PDT 24 |
221731800 ps |
| T1107 |
/workspace/coverage/default/2.flash_ctrl_intr_rd.4137132137 |
|
|
Apr 02 03:24:15 PM PDT 24 |
Apr 02 03:26:44 PM PDT 24 |
2054031600 ps |
| T1108 |
/workspace/coverage/default/5.flash_ctrl_alert_test.375317314 |
|
|
Apr 02 03:25:10 PM PDT 24 |
Apr 02 03:25:24 PM PDT 24 |
84344800 ps |
| T1109 |
/workspace/coverage/default/7.flash_ctrl_alert_test.3677759110 |
|
|
Apr 02 03:25:35 PM PDT 24 |
Apr 02 03:25:49 PM PDT 24 |
55272700 ps |
| T1110 |
/workspace/coverage/default/9.flash_ctrl_phy_arb.2947039246 |
|
|
Apr 02 03:25:56 PM PDT 24 |
Apr 02 03:37:31 PM PDT 24 |
13436397700 ps |
| T192 |
/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3653841935 |
|
|
Apr 02 03:24:30 PM PDT 24 |
Apr 02 03:24:46 PM PDT 24 |
43503300 ps |
| T1111 |
/workspace/coverage/default/7.flash_ctrl_mp_regions.3637225207 |
|
|
Apr 02 03:25:23 PM PDT 24 |
Apr 02 03:35:37 PM PDT 24 |
8931301300 ps |
| T1112 |
/workspace/coverage/default/48.flash_ctrl_disable.3178583319 |
|
|
Apr 02 03:31:02 PM PDT 24 |
Apr 02 03:31:24 PM PDT 24 |
13508300 ps |
| T1113 |
/workspace/coverage/default/13.flash_ctrl_invalid_op.2620902779 |
|
|
Apr 02 03:26:57 PM PDT 24 |
Apr 02 03:28:07 PM PDT 24 |
4144061000 ps |
| T1114 |
/workspace/coverage/default/2.flash_ctrl_erase_suspend.979871804 |
|
|
Apr 02 03:24:11 PM PDT 24 |
Apr 02 03:29:08 PM PDT 24 |
14777981300 ps |
| T1115 |
/workspace/coverage/default/23.flash_ctrl_intr_rd.694583535 |
|
|
Apr 02 03:28:54 PM PDT 24 |
Apr 02 03:31:48 PM PDT 24 |
4551967800 ps |
| T1116 |
/workspace/coverage/default/11.flash_ctrl_rw_evict.1599205602 |
|
|
Apr 02 03:26:36 PM PDT 24 |
Apr 02 03:27:11 PM PDT 24 |
174560900 ps |
| T1117 |
/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1791358219 |
|
|
Apr 02 03:24:28 PM PDT 24 |
Apr 02 03:26:14 PM PDT 24 |
135624400 ps |
| T1118 |
/workspace/coverage/default/12.flash_ctrl_rw.2903625508 |
|
|
Apr 02 03:26:43 PM PDT 24 |
Apr 02 03:35:38 PM PDT 24 |
3077594000 ps |
| T1119 |
/workspace/coverage/default/14.flash_ctrl_rw.4239006909 |
|
|
Apr 02 03:27:14 PM PDT 24 |
Apr 02 03:35:30 PM PDT 24 |
6100164600 ps |
| T1120 |
/workspace/coverage/default/32.flash_ctrl_rw_evict.1697403038 |
|
|
Apr 02 03:29:49 PM PDT 24 |
Apr 02 03:30:18 PM PDT 24 |
40108000 ps |
| T1121 |
/workspace/coverage/default/39.flash_ctrl_rw_evict.1019765916 |
|
|
Apr 02 03:30:29 PM PDT 24 |
Apr 02 03:31:02 PM PDT 24 |
48876400 ps |
| T1122 |
/workspace/coverage/default/25.flash_ctrl_sec_info_access.1435807072 |
|
|
Apr 02 03:29:11 PM PDT 24 |
Apr 02 03:30:34 PM PDT 24 |
2299330800 ps |
| T1123 |
/workspace/coverage/default/5.flash_ctrl_prog_reset.3846339246 |
|
|
Apr 02 03:25:06 PM PDT 24 |
Apr 02 03:25:19 PM PDT 24 |
179415500 ps |
| T1124 |
/workspace/coverage/default/18.flash_ctrl_rw_evict.2626920775 |
|
|
Apr 02 03:28:08 PM PDT 24 |
Apr 02 03:28:38 PM PDT 24 |
43139400 ps |
| T1125 |
/workspace/coverage/default/1.flash_ctrl_disable.4134400097 |
|
|
Apr 02 03:24:08 PM PDT 24 |
Apr 02 03:24:29 PM PDT 24 |
37675100 ps |
| T1126 |
/workspace/coverage/default/15.flash_ctrl_rw_evict.3271623328 |
|
|
Apr 02 03:27:26 PM PDT 24 |
Apr 02 03:27:59 PM PDT 24 |
412759300 ps |
| T1127 |
/workspace/coverage/default/74.flash_ctrl_connect.3920603488 |
|
|
Apr 02 03:31:29 PM PDT 24 |
Apr 02 03:31:46 PM PDT 24 |
71328400 ps |
| T1128 |
/workspace/coverage/default/7.flash_ctrl_disable.1312652438 |
|
|
Apr 02 03:25:33 PM PDT 24 |
Apr 02 03:25:54 PM PDT 24 |
21671500 ps |
| T1129 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1188034350 |
|
|
Apr 02 03:23:49 PM PDT 24 |
Apr 02 03:26:09 PM PDT 24 |
2805133500 ps |
| T1130 |
/workspace/coverage/default/18.flash_ctrl_rw.3038594221 |
|
|
Apr 02 03:28:05 PM PDT 24 |
Apr 02 03:37:03 PM PDT 24 |
22033456000 ps |
| T1131 |
/workspace/coverage/default/11.flash_ctrl_wo.992087791 |
|
|
Apr 02 03:26:33 PM PDT 24 |
Apr 02 03:29:03 PM PDT 24 |
18228213200 ps |
| T1132 |
/workspace/coverage/default/7.flash_ctrl_fetch_code.541711142 |
|
|
Apr 02 03:25:23 PM PDT 24 |
Apr 02 03:25:49 PM PDT 24 |
1090486200 ps |
| T306 |
/workspace/coverage/default/10.flash_ctrl_intr_rd.2419409031 |
|
|
Apr 02 03:26:19 PM PDT 24 |
Apr 02 03:30:02 PM PDT 24 |
4562152500 ps |
| T1133 |
/workspace/coverage/default/78.flash_ctrl_otp_reset.3794227975 |
|
|
Apr 02 03:31:34 PM PDT 24 |
Apr 02 03:33:46 PM PDT 24 |
134250700 ps |
| T1134 |
/workspace/coverage/default/12.flash_ctrl_otp_reset.3891010529 |
|
|
Apr 02 03:26:42 PM PDT 24 |
Apr 02 03:28:54 PM PDT 24 |
166032000 ps |
| T1135 |
/workspace/coverage/default/8.flash_ctrl_smoke.312700050 |
|
|
Apr 02 03:25:36 PM PDT 24 |
Apr 02 03:28:51 PM PDT 24 |
78214000 ps |
| T248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2565672160 |
|
|
Apr 02 12:43:40 PM PDT 24 |
Apr 02 12:43:54 PM PDT 24 |
27996300 ps |
| T249 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.587333112 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:15 PM PDT 24 |
17726300 ps |
| T60 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3152058611 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:58:55 PM PDT 24 |
1070663600 ps |
| T61 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1538593713 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
25466200 ps |
| T250 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3070215689 |
|
|
Apr 02 12:43:40 PM PDT 24 |
Apr 02 12:43:54 PM PDT 24 |
49688300 ps |
| T170 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4060466332 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:44:03 PM PDT 24 |
56867000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1549110493 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
44196200 ps |
| T173 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2192482433 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
201126700 ps |
| T300 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.301974502 |
|
|
Apr 02 12:44:10 PM PDT 24 |
Apr 02 12:44:24 PM PDT 24 |
65613200 ps |
| T62 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4005907045 |
|
|
Apr 02 12:43:45 PM PDT 24 |
Apr 02 12:44:31 PM PDT 24 |
92536700 ps |
| T171 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1997137933 |
|
|
Apr 02 12:43:38 PM PDT 24 |
Apr 02 12:43:56 PM PDT 24 |
64192600 ps |
| T208 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2014496867 |
|
|
Apr 02 12:44:00 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
107011800 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2241677210 |
|
|
Apr 02 12:43:38 PM PDT 24 |
Apr 02 12:43:52 PM PDT 24 |
134882900 ps |
| T209 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2955838960 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
34002200 ps |
| T299 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1838023322 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:44:01 PM PDT 24 |
17392000 ps |
| T237 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1262159203 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:44:04 PM PDT 24 |
71081900 ps |
| T1137 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1160545559 |
|
|
Apr 02 12:43:41 PM PDT 24 |
Apr 02 12:43:57 PM PDT 24 |
35789800 ps |
| T301 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1080979437 |
|
|
Apr 02 12:44:06 PM PDT 24 |
Apr 02 12:44:20 PM PDT 24 |
18653900 ps |
| T303 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2548714755 |
|
|
Apr 02 12:44:07 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
127941800 ps |
| T242 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1018785583 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
64568300 ps |
| T1138 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2037753638 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:44:10 PM PDT 24 |
51885000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4005884539 |
|
|
Apr 02 12:44:13 PM PDT 24 |
Apr 02 12:44:27 PM PDT 24 |
25674000 ps |
| T172 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1963278497 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
37493200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2059990381 |
|
|
Apr 02 12:44:11 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
45957400 ps |
| T243 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.433361017 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:04 PM PDT 24 |
49646900 ps |
| T1141 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1920254075 |
|
|
Apr 02 12:43:45 PM PDT 24 |
Apr 02 12:44:00 PM PDT 24 |
104007700 ps |
| T244 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2875427433 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:08 PM PDT 24 |
122282200 ps |
| T221 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.554242219 |
|
|
Apr 02 12:44:06 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
51495100 ps |
| T1142 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2716951718 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:15 PM PDT 24 |
15891600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2708769170 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
24240300 ps |
| T222 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2008717732 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:44:22 PM PDT 24 |
28232800 ps |
| T207 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4042389801 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:22 PM PDT 24 |
42708000 ps |
| T1144 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1320058844 |
|
|
Apr 02 12:43:51 PM PDT 24 |
Apr 02 12:44:07 PM PDT 24 |
37556600 ps |
| T223 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2169265288 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
46081100 ps |
| T1145 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3558746537 |
|
|
Apr 02 12:43:52 PM PDT 24 |
Apr 02 12:44:08 PM PDT 24 |
341718700 ps |
| T357 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4064262797 |
|
|
Apr 02 12:43:56 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
28363500 ps |
| T224 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2169327228 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:04 PM PDT 24 |
18281400 ps |
| T238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1926687556 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:51:19 PM PDT 24 |
346767900 ps |
| T280 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1496740060 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
39756800 ps |
| T1146 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3744095650 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
14427000 ps |
| T239 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3764212453 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:59:01 PM PDT 24 |
3712701800 ps |
| T273 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1609551706 |
|
|
Apr 02 12:43:45 PM PDT 24 |
Apr 02 12:44:05 PM PDT 24 |
182973000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.383676768 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:16 PM PDT 24 |
108892000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1447896284 |
|
|
Apr 02 12:44:15 PM PDT 24 |
Apr 02 12:44:29 PM PDT 24 |
48575500 ps |
| T395 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.140796120 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:06 PM PDT 24 |
72973500 ps |
| T245 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4124429045 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
74900500 ps |
| T1149 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1734299762 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
134294600 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.462243661 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:44:01 PM PDT 24 |
196564500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.121787388 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
142555400 ps |
| T1151 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1733749304 |
|
|
Apr 02 12:44:11 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
51172800 ps |
| T1152 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3451461023 |
|
|
Apr 02 12:43:57 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
24065500 ps |
| T396 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2619805798 |
|
|
Apr 02 12:43:56 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
201187300 ps |
| T302 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3916666640 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
194517100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.769242817 |
|
|
Apr 02 12:44:08 PM PDT 24 |
Apr 02 12:44:22 PM PDT 24 |
15497300 ps |
| T346 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.697155817 |
|
|
Apr 02 12:43:44 PM PDT 24 |
Apr 02 12:51:22 PM PDT 24 |
322296100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3990282524 |
|
|
Apr 02 12:43:45 PM PDT 24 |
Apr 02 12:44:01 PM PDT 24 |
20239200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3458629263 |
|
|
Apr 02 12:43:44 PM PDT 24 |
Apr 02 12:43:59 PM PDT 24 |
19953000 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3344161543 |
|
|
Apr 02 12:43:40 PM PDT 24 |
Apr 02 12:43:56 PM PDT 24 |
17732100 ps |
| T1157 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2591362887 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
676255300 ps |
| T252 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2638226771 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
79494000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.325910529 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:43:56 PM PDT 24 |
25180200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2471031423 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
57674400 ps |
| T251 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1001913030 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:44:00 PM PDT 24 |
90146500 ps |
| T1160 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4191283530 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:11 PM PDT 24 |
14685200 ps |
| T274 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3816270164 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:51:43 PM PDT 24 |
1542969700 ps |
| T275 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1988988962 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:22 PM PDT 24 |
111187300 ps |
| T1161 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.703412360 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:44:03 PM PDT 24 |
18374600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2894482668 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
39472500 ps |
| T225 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2560131891 |
|
|
Apr 02 12:43:44 PM PDT 24 |
Apr 02 12:43:58 PM PDT 24 |
30692200 ps |
| T1163 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2860667997 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:01 PM PDT 24 |
54442400 ps |
| T276 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.486799328 |
|
|
Apr 02 12:43:44 PM PDT 24 |
Apr 02 12:43:59 PM PDT 24 |
110265500 ps |
| T344 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3178525353 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:56:35 PM PDT 24 |
1704341900 ps |
| T1164 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.746767583 |
|
|
Apr 02 12:44:00 PM PDT 24 |
Apr 02 12:44:16 PM PDT 24 |
27735400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.839480927 |
|
|
Apr 02 12:43:56 PM PDT 24 |
Apr 02 12:44:15 PM PDT 24 |
57232800 ps |
| T1166 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1365328554 |
|
|
Apr 02 12:44:00 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
133685700 ps |
| T350 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2115202253 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:51:32 PM PDT 24 |
692102400 ps |
| T1167 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2327815035 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
35755100 ps |
| T1168 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.91791941 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:23 PM PDT 24 |
62268200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1178151103 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:44:42 PM PDT 24 |
46605900 ps |
| T247 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4253410174 |
|
|
Apr 02 12:44:10 PM PDT 24 |
Apr 02 12:44:27 PM PDT 24 |
28956300 ps |
| T1170 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3412422548 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:03 PM PDT 24 |
44247900 ps |
| T352 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1914634491 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:51:32 PM PDT 24 |
821672100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1820082795 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
49572700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1403533392 |
|
|
Apr 02 12:44:06 PM PDT 24 |
Apr 02 12:44:20 PM PDT 24 |
61079000 ps |
| T1173 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3043525442 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
45595900 ps |
| T1174 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1831704871 |
|
|
Apr 02 12:43:52 PM PDT 24 |
Apr 02 12:44:08 PM PDT 24 |
69910800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2023768754 |
|
|
Apr 02 12:43:38 PM PDT 24 |
Apr 02 12:43:51 PM PDT 24 |
25927200 ps |
| T354 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1422833067 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:50:35 PM PDT 24 |
376984100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3756872618 |
|
|
Apr 02 12:43:37 PM PDT 24 |
Apr 02 12:44:43 PM PDT 24 |
2052354900 ps |
| T281 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3609963759 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:02 PM PDT 24 |
62849800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4074002374 |
|
|
Apr 02 12:44:08 PM PDT 24 |
Apr 02 12:44:28 PM PDT 24 |
91052300 ps |
| T277 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2183183136 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
41629900 ps |
| T1178 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1579850087 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
30397100 ps |
| T278 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3926737780 |
|
|
Apr 02 12:43:40 PM PDT 24 |
Apr 02 12:43:58 PM PDT 24 |
198287100 ps |
| T1179 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3301555943 |
|
|
Apr 02 12:44:13 PM PDT 24 |
Apr 02 12:44:27 PM PDT 24 |
14544300 ps |
| T341 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3701596026 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:56:22 PM PDT 24 |
656778900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3494805799 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:27 PM PDT 24 |
342929200 ps |
| T342 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1504097088 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:59:04 PM PDT 24 |
2858300800 ps |
| T1181 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2308475772 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
331067800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.149409745 |
|
|
Apr 02 12:43:39 PM PDT 24 |
Apr 02 12:43:54 PM PDT 24 |
14434600 ps |
| T1183 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2017355808 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:06 PM PDT 24 |
335576300 ps |
| T1184 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4266357141 |
|
|
Apr 02 12:43:49 PM PDT 24 |
Apr 02 12:44:22 PM PDT 24 |
239807900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3918972767 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:09 PM PDT 24 |
57491900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3914028535 |
|
|
Apr 02 12:44:12 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
27309000 ps |
| T1187 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2009851517 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
16049200 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.461397776 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
67816900 ps |
| T351 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2026288523 |
|
|
Apr 02 12:43:34 PM PDT 24 |
Apr 02 12:58:37 PM PDT 24 |
364932000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2590758024 |
|
|
Apr 02 12:43:52 PM PDT 24 |
Apr 02 12:44:06 PM PDT 24 |
119102100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1194707848 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
18005600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3816522670 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
115891800 ps |
| T1192 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2298475601 |
|
|
Apr 02 12:43:46 PM PDT 24 |
Apr 02 12:44:02 PM PDT 24 |
23581400 ps |
| T279 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.649243946 |
|
|
Apr 02 12:44:08 PM PDT 24 |
Apr 02 12:44:28 PM PDT 24 |
556769600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.650514459 |
|
|
Apr 02 12:43:57 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
114129700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1737807935 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
115231700 ps |
| T1195 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2439825983 |
|
|
Apr 02 12:44:13 PM PDT 24 |
Apr 02 12:44:27 PM PDT 24 |
15836100 ps |
| T343 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.329492579 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:51:38 PM PDT 24 |
1319495200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.138316785 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:15 PM PDT 24 |
14164800 ps |
| T1197 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.54155186 |
|
|
Apr 02 12:44:06 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
20186800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.383729644 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
125270400 ps |
| T1199 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3141398104 |
|
|
Apr 02 12:43:41 PM PDT 24 |
Apr 02 12:43:58 PM PDT 24 |
37083900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4111045093 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
24271500 ps |
| T1201 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3140306814 |
|
|
Apr 02 12:43:41 PM PDT 24 |
Apr 02 12:43:58 PM PDT 24 |
459554300 ps |
| T1202 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.173253935 |
|
|
Apr 02 12:43:49 PM PDT 24 |
Apr 02 12:44:05 PM PDT 24 |
256609200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.518667175 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
141742700 ps |
| T1204 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1271471331 |
|
|
Apr 02 12:44:06 PM PDT 24 |
Apr 02 12:44:20 PM PDT 24 |
19639300 ps |
| T1205 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2364329982 |
|
|
Apr 02 12:43:57 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
36545600 ps |
| T1206 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3450475403 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
15528900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3858919157 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
25193300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4102724632 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:04 PM PDT 24 |
11671300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.748412632 |
|
|
Apr 02 12:44:00 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
14584600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2447131476 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:07 PM PDT 24 |
45200100 ps |
| T347 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3799204205 |
|
|
Apr 02 12:43:46 PM PDT 24 |
Apr 02 12:58:43 PM PDT 24 |
746597600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.422704479 |
|
|
Apr 02 12:44:15 PM PDT 24 |
Apr 02 12:44:31 PM PDT 24 |
203280000 ps |
| T1212 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3741838291 |
|
|
Apr 02 12:43:46 PM PDT 24 |
Apr 02 12:44:02 PM PDT 24 |
24674700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.873011576 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:44:20 PM PDT 24 |
21378700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1139197339 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
86396400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3872958623 |
|
|
Apr 02 12:44:08 PM PDT 24 |
Apr 02 12:44:23 PM PDT 24 |
46737200 ps |
| T1216 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.562600349 |
|
|
Apr 02 12:43:41 PM PDT 24 |
Apr 02 12:44:36 PM PDT 24 |
2372498000 ps |
| T340 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3627359541 |
|
|
Apr 02 12:43:36 PM PDT 24 |
Apr 02 12:43:56 PM PDT 24 |
52870300 ps |
| T1217 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3704773607 |
|
|
Apr 02 12:44:13 PM PDT 24 |
Apr 02 12:44:31 PM PDT 24 |
41704300 ps |
| T1218 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1076870039 |
|
|
Apr 02 12:43:48 PM PDT 24 |
Apr 02 12:44:03 PM PDT 24 |
25719100 ps |
| T1219 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2922694720 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:18 PM PDT 24 |
47693400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2180228591 |
|
|
Apr 02 12:43:38 PM PDT 24 |
Apr 02 12:43:51 PM PDT 24 |
14137400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1479985396 |
|
|
Apr 02 12:44:09 PM PDT 24 |
Apr 02 12:44:23 PM PDT 24 |
31764000 ps |
| T226 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2646557224 |
|
|
Apr 02 12:43:44 PM PDT 24 |
Apr 02 12:43:58 PM PDT 24 |
15700400 ps |
| T1222 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.988165786 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:20 PM PDT 24 |
110741700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3686515672 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
58042000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.748153759 |
|
|
Apr 02 12:43:51 PM PDT 24 |
Apr 02 12:44:08 PM PDT 24 |
99733300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.286204444 |
|
|
Apr 02 12:43:38 PM PDT 24 |
Apr 02 12:43:55 PM PDT 24 |
30269400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2635015913 |
|
|
Apr 02 12:43:56 PM PDT 24 |
Apr 02 12:44:12 PM PDT 24 |
22051000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3995606442 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
41585900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4154223153 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:45:02 PM PDT 24 |
4676116200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3888611934 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:43:56 PM PDT 24 |
43040500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1226901889 |
|
|
Apr 02 12:43:42 PM PDT 24 |
Apr 02 12:44:28 PM PDT 24 |
26445200 ps |
| T1231 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2679537427 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:44:37 PM PDT 24 |
2914799900 ps |
| T1232 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1677216710 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:44:19 PM PDT 24 |
48519700 ps |
| T349 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1579366022 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:58:53 PM PDT 24 |
1414003800 ps |
| T283 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1020254 |
|
|
Apr 02 12:44:11 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
40852500 ps |
| T284 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.796642296 |
|
|
Apr 02 12:43:37 PM PDT 24 |
Apr 02 12:44:09 PM PDT 24 |
35013000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1843012210 |
|
|
Apr 02 12:43:41 PM PDT 24 |
Apr 02 12:43:54 PM PDT 24 |
17060800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3826715754 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:09 PM PDT 24 |
70153400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2448747187 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
138730600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.114723745 |
|
|
Apr 02 12:43:50 PM PDT 24 |
Apr 02 12:44:03 PM PDT 24 |
22948800 ps |
| T1237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1375941765 |
|
|
Apr 02 12:44:03 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
86277300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4109341362 |
|
|
Apr 02 12:44:09 PM PDT 24 |
Apr 02 12:44:26 PM PDT 24 |
119491900 ps |
| T282 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.7213654 |
|
|
Apr 02 12:43:46 PM PDT 24 |
Apr 02 12:45:11 PM PDT 24 |
6694182000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.421842402 |
|
|
Apr 02 12:44:06 PM PDT 24 |
Apr 02 12:44:23 PM PDT 24 |
201282600 ps |
| T1240 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2920810249 |
|
|
Apr 02 12:44:07 PM PDT 24 |
Apr 02 12:44:21 PM PDT 24 |
30432100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.835791588 |
|
|
Apr 02 12:43:59 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
16571400 ps |
| T227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3413150006 |
|
|
Apr 02 12:43:40 PM PDT 24 |
Apr 02 12:43:54 PM PDT 24 |
94955200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4058534910 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:44:11 PM PDT 24 |
44270200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1342721148 |
|
|
Apr 02 12:43:43 PM PDT 24 |
Apr 02 12:43:57 PM PDT 24 |
18157700 ps |
| T1244 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2857312802 |
|
|
Apr 02 12:43:54 PM PDT 24 |
Apr 02 12:44:14 PM PDT 24 |
179585000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3389262069 |
|
|
Apr 02 12:43:49 PM PDT 24 |
Apr 02 12:44:04 PM PDT 24 |
581115100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1158616319 |
|
|
Apr 02 12:44:04 PM PDT 24 |
Apr 02 12:51:46 PM PDT 24 |
362985400 ps |
| T348 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1202804197 |
|
|
Apr 02 12:44:01 PM PDT 24 |
Apr 02 12:51:43 PM PDT 24 |
191716300 ps |
| T345 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3073405582 |
|
|
Apr 02 12:43:47 PM PDT 24 |
Apr 02 12:51:23 PM PDT 24 |
612199200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.40990025 |
|
|
Apr 02 12:44:21 PM PDT 24 |
Apr 02 12:44:34 PM PDT 24 |
91257000 ps |
| T1248 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1450078330 |
|
|
Apr 02 12:44:10 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
71808400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.151508551 |
|
|
Apr 02 12:44:00 PM PDT 24 |
Apr 02 12:44:17 PM PDT 24 |
28813100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.42615962 |
|
|
Apr 02 12:43:49 PM PDT 24 |
Apr 02 12:44:06 PM PDT 24 |
87819800 ps |
| T1251 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1185150021 |
|
|
Apr 02 12:44:13 PM PDT 24 |
Apr 02 12:44:27 PM PDT 24 |
79184300 ps |
| T1252 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2057054682 |
|
|
Apr 02 12:43:39 PM PDT 24 |
Apr 02 12:44:29 PM PDT 24 |
1709728600 ps |
| T1253 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1373086530 |
|
|
Apr 02 12:44:02 PM PDT 24 |
Apr 02 12:44:16 PM PDT 24 |
61612200 ps |
| T1254 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1225710347 |
|
|
Apr 02 12:43:58 PM PDT 24 |
Apr 02 12:44:13 PM PDT 24 |
15632200 ps |
| T353 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2212120746 |
|
|
Apr 02 12:44:05 PM PDT 24 |
Apr 02 12:59:14 PM PDT 24 |
1511164700 ps |
| T1255 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2095474513 |
|
|
Apr 02 12:44:11 PM PDT 24 |
Apr 02 12:44:25 PM PDT 24 |
45714100 ps |