Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	310357	1		T1	2		T3	1		T4	1
all_values[1]	310357	1		T1	2		T3	1		T4	1
all_values[2]	310357	1		T1	2		T3	1		T4	1
all_values[3]	310357	1		T1	2		T3	1		T4	1
all_values[4]	310357	1		T1	2		T3	1		T4	1
all_values[5]	310357	1		T1	2		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	627131	1		T1	12		T3	6		T4	6
auto[1]	1235011	1		T6	6384		T29	14192		T19	10008

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	916654	1		T1	7		T3	4		T4	4
auto[1]	945488	1		T1	5		T3	2		T4	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	310208	1		T1	2		T3	1		T4	1
all_values[0]	auto[1]	auto[1]	149	1		T264	5		T265	1		T266	2
all_values[1]	auto[0]	auto[1]	310219	1		T1	2		T3	1		T4	1
all_values[1]	auto[1]	auto[1]	138	1		T265	5		T266	5		T325	3
all_values[2]	auto[0]	auto[0]	1616	1		T1	2		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	54	1		T266	2		T325	1		T327	2
all_values[2]	auto[1]	auto[0]	308628	1		T6	1596		T29	3548		T19	2502
all_values[2]	auto[1]	auto[1]	59	1		T264	1		T265	1		T325	1
all_values[3]	auto[0]	auto[0]	1615	1		T1	2		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	63	1		T264	2		T265	1		T325	1
all_values[3]	auto[1]	auto[0]	83279	1		T19	834		T21	1155		T224	1142
all_values[3]	auto[1]	auto[1]	225400	1		T6	1596		T29	3548		T19	1668
all_values[4]	auto[0]	auto[0]	1159	1		T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	521	1		T1	1		T16	1		T7	1
all_values[4]	auto[1]	auto[0]	210193	1		T6	798		T29	2661		T19	1668
all_values[4]	auto[1]	auto[1]	98484	1		T6	798		T29	887		T19	834
all_values[5]	auto[0]	auto[0]	1544	1		T1	2		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	132	1		T7	1		T31	1		T32	1
all_values[5]	auto[1]	auto[0]	308620	1		T6	1596		T29	3548		T19	2502
all_values[5]	auto[1]	auto[1]	61	1		T265	2		T266	1		T327	2