Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T79 |
7 |
|
T88 |
7 |
|
T234 |
1 |
| others[1] |
205 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T79 |
7 |
| others[2] |
229 |
1 |
|
T79 |
8 |
|
T88 |
9 |
|
T374 |
1 |
| others[3] |
404 |
1 |
|
T7 |
1 |
|
T72 |
1 |
|
T79 |
16 |
| false |
129 |
1 |
|
T79 |
7 |
|
T88 |
4 |
|
T225 |
1 |
| true |
13096 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T79 |
10 |
|
T104 |
1 |
|
T88 |
14 |
| others[1] |
197 |
1 |
|
T18 |
1 |
|
T79 |
9 |
|
T88 |
7 |
| others[2] |
228 |
1 |
|
T79 |
9 |
|
T88 |
13 |
|
T90 |
10 |
| others[3] |
362 |
1 |
|
T72 |
1 |
|
T79 |
13 |
|
T88 |
15 |
| false |
99 |
1 |
|
T79 |
5 |
|
T88 |
7 |
|
T90 |
6 |
| true |
13173 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8667 |
1 |
|
T6 |
1 |
|
T59 |
17 |
|
T13 |
2 |
| others[1] |
1280 |
1 |
|
T2 |
1 |
|
T59 |
20 |
|
T8 |
1 |
| others[2] |
1173 |
1 |
|
T59 |
18 |
|
T42 |
1 |
|
T79 |
14 |
| others[3] |
2149 |
1 |
|
T16 |
1 |
|
T59 |
35 |
|
T60 |
1 |
| false |
588 |
1 |
|
T59 |
10 |
|
T79 |
10 |
|
T88 |
9 |
| true |
434 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8664 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
17 |
| others[1] |
1232 |
1 |
|
T6 |
1 |
|
T59 |
19 |
|
T79 |
15 |
| others[2] |
1296 |
1 |
|
T3 |
1 |
|
T59 |
29 |
|
T8 |
1 |
| others[3] |
2015 |
1 |
|
T59 |
30 |
|
T60 |
1 |
|
T79 |
28 |
| false |
655 |
1 |
|
T59 |
5 |
|
T42 |
1 |
|
T79 |
17 |
| true |
429 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T227 |
1 |
|
T79 |
3 |
|
T88 |
1 |
| others[1] |
116 |
1 |
|
T18 |
1 |
|
T79 |
3 |
|
T88 |
8 |
| others[2] |
109 |
1 |
|
T16 |
1 |
|
T79 |
3 |
|
T88 |
3 |
| others[3] |
170 |
1 |
|
T72 |
1 |
|
T79 |
4 |
|
T88 |
5 |
| false |
60 |
1 |
|
T79 |
4 |
|
T88 |
1 |
|
T373 |
1 |
| true |
13740 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T79 |
8 |
| others[1] |
244 |
1 |
|
T79 |
10 |
|
T88 |
12 |
|
T225 |
1 |
| others[2] |
235 |
1 |
|
T16 |
1 |
|
T72 |
1 |
|
T227 |
1 |
| others[3] |
383 |
1 |
|
T61 |
1 |
|
T79 |
10 |
|
T88 |
9 |
| false |
144 |
1 |
|
T79 |
2 |
|
T88 |
6 |
|
T197 |
1 |
| true |
13061 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8485 |
1 |
|
T59 |
10 |
|
T13 |
2 |
|
T60 |
1 |
| others[1] |
1081 |
1 |
|
T59 |
12 |
|
T20 |
1 |
|
T79 |
25 |
| others[2] |
1062 |
1 |
|
T4 |
1 |
|
T59 |
11 |
|
T12 |
1 |
| others[3] |
1754 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| false |
520 |
1 |
|
T59 |
3 |
|
T79 |
11 |
|
T44 |
1 |
| true |
1389 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T17 |
1 |
|
T79 |
8 |
|
T88 |
7 |
| others[1] |
251 |
1 |
|
T4 |
1 |
|
T72 |
1 |
|
T79 |
13 |
| others[2] |
230 |
1 |
|
T79 |
15 |
|
T88 |
6 |
|
T55 |
1 |
| others[3] |
386 |
1 |
|
T18 |
1 |
|
T227 |
1 |
|
T79 |
17 |
| false |
119 |
1 |
|
T79 |
4 |
|
T88 |
4 |
|
T125 |
1 |
| true |
13056 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T18 |
1 |
|
T79 |
14 |
|
T88 |
12 |
| others[1] |
230 |
1 |
|
T79 |
10 |
|
T104 |
1 |
|
T88 |
12 |
| others[2] |
227 |
1 |
|
T79 |
8 |
|
T88 |
11 |
|
T234 |
1 |
| others[3] |
337 |
1 |
|
T227 |
1 |
|
T79 |
17 |
|
T88 |
18 |
| false |
116 |
1 |
|
T79 |
5 |
|
T88 |
2 |
|
T373 |
1 |
| true |
13128 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8699 |
1 |
|
T59 |
21 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
1253 |
1 |
|
T59 |
17 |
|
T79 |
18 |
|
T44 |
1 |
| others[2] |
1261 |
1 |
|
T59 |
22 |
|
T109 |
1 |
|
T42 |
1 |
| others[3] |
2041 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| false |
605 |
1 |
|
T2 |
1 |
|
T59 |
10 |
|
T8 |
1 |
| true |
432 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T59 |
23 |
|
T8 |
1 |
|
T79 |
15 |
| others[1] |
1183 |
1 |
|
T2 |
1 |
|
T59 |
18 |
|
T79 |
20 |
| others[2] |
1252 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T18 |
1 |
| others[3] |
2109 |
1 |
|
T59 |
33 |
|
T42 |
3 |
|
T29 |
1 |
| false |
654 |
1 |
|
T59 |
4 |
|
T79 |
11 |
|
T88 |
10 |
| true |
427 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T79 |
4 |
|
T88 |
1 |
|
T45 |
1 |
| others[1] |
97 |
1 |
|
T79 |
2 |
|
T88 |
4 |
|
T90 |
6 |
| others[2] |
102 |
1 |
|
T79 |
6 |
|
T104 |
1 |
|
T88 |
3 |
| others[3] |
146 |
1 |
|
T79 |
3 |
|
T88 |
9 |
|
T375 |
1 |
| false |
54 |
1 |
|
T88 |
2 |
|
T234 |
1 |
|
T90 |
3 |
| true |
6364 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T3 |
1 |
|
T79 |
13 |
|
T104 |
1 |
| others[1] |
221 |
1 |
|
T79 |
6 |
|
T88 |
10 |
|
T373 |
1 |
| others[2] |
241 |
1 |
|
T79 |
11 |
|
T88 |
9 |
|
T54 |
1 |
| others[3] |
404 |
1 |
|
T17 |
1 |
|
T227 |
1 |
|
T79 |
21 |
| false |
146 |
1 |
|
T79 |
6 |
|
T88 |
7 |
|
T197 |
1 |
| true |
5628 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[1] |
1087 |
1 |
|
T18 |
1 |
|
T59 |
13 |
|
T79 |
13 |
| others[2] |
1061 |
1 |
|
T59 |
7 |
|
T8 |
1 |
|
T42 |
1 |
| others[3] |
1733 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T59 |
18 |
| false |
533 |
1 |
|
T2 |
1 |
|
T59 |
6 |
|
T109 |
1 |
| true |
1406 |
1 |
|
T17 |
1 |
|
T59 |
49 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
263 |
1 |
|
T79 |
9 |
|
T88 |
13 |
|
T234 |
1 |
| others[1] |
237 |
1 |
|
T79 |
9 |
|
T88 |
13 |
|
T33 |
1 |
| others[2] |
246 |
1 |
|
T79 |
12 |
|
T104 |
1 |
|
T88 |
9 |
| others[3] |
361 |
1 |
|
T227 |
1 |
|
T79 |
18 |
|
T88 |
16 |
| false |
116 |
1 |
|
T72 |
1 |
|
T79 |
1 |
|
T88 |
5 |
| true |
5639 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T79 |
14 |
|
T88 |
6 |
|
T45 |
1 |
| others[1] |
210 |
1 |
|
T79 |
7 |
|
T88 |
6 |
|
T374 |
1 |
| others[2] |
211 |
1 |
|
T7 |
1 |
|
T79 |
5 |
|
T88 |
9 |
| others[3] |
361 |
1 |
|
T18 |
1 |
|
T79 |
12 |
|
T88 |
22 |
| false |
116 |
1 |
|
T79 |
6 |
|
T88 |
4 |
|
T55 |
1 |
| true |
5735 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T59 |
23 |
|
T8 |
1 |
|
T79 |
22 |
| others[1] |
1213 |
1 |
|
T16 |
1 |
|
T59 |
20 |
|
T42 |
1 |
| others[2] |
1292 |
1 |
|
T6 |
1 |
|
T59 |
17 |
|
T109 |
1 |
| others[3] |
2038 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T59 |
30 |
| false |
644 |
1 |
|
T59 |
10 |
|
T42 |
1 |
|
T79 |
14 |
| true |
437 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T59 |
24 |
|
T60 |
1 |
|
T8 |
1 |
| others[1] |
1235 |
1 |
|
T59 |
22 |
|
T42 |
1 |
|
T79 |
24 |
| others[2] |
1269 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T59 |
17 |
| others[3] |
2089 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T59 |
29 |
| false |
636 |
1 |
|
T3 |
1 |
|
T59 |
8 |
|
T109 |
1 |
| true |
427 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T79 |
2 |
|
T88 |
3 |
|
T90 |
2 |
| others[1] |
91 |
1 |
|
T79 |
2 |
|
T88 |
5 |
|
T374 |
1 |
| others[2] |
106 |
1 |
|
T79 |
6 |
|
T88 |
3 |
|
T237 |
1 |
| others[3] |
165 |
1 |
|
T79 |
7 |
|
T88 |
8 |
|
T90 |
1 |
| false |
58 |
1 |
|
T79 |
1 |
|
T88 |
2 |
|
T234 |
1 |
| true |
6325 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T79 |
5 |
|
T88 |
13 |
|
T373 |
1 |
| others[1] |
248 |
1 |
|
T72 |
1 |
|
T79 |
13 |
|
T88 |
9 |
| others[2] |
236 |
1 |
|
T79 |
6 |
|
T88 |
10 |
|
T197 |
1 |
| others[3] |
407 |
1 |
|
T16 |
1 |
|
T79 |
15 |
|
T88 |
11 |
| false |
108 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T79 |
6 |
| true |
5647 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T59 |
12 |
|
T79 |
13 |
|
T88 |
17 |
| others[1] |
1046 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T17 |
1 |
| others[2] |
1071 |
1 |
|
T59 |
11 |
|
T8 |
1 |
|
T227 |
1 |
| others[3] |
1742 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T18 |
1 |
| false |
549 |
1 |
|
T59 |
2 |
|
T79 |
13 |
|
T88 |
7 |
| true |
1393 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T59 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T7 |
1 |
|
T79 |
6 |
|
T88 |
11 |
| others[1] |
239 |
1 |
|
T79 |
11 |
|
T88 |
4 |
|
T234 |
1 |
| others[2] |
233 |
1 |
|
T17 |
1 |
|
T227 |
1 |
|
T79 |
9 |
| others[3] |
369 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T72 |
1 |
| false |
127 |
1 |
|
T16 |
1 |
|
T79 |
5 |
|
T88 |
5 |
| true |
5668 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T16 |
1 |
|
T79 |
9 |
|
T88 |
11 |
| others[1] |
222 |
1 |
|
T79 |
9 |
|
T88 |
12 |
|
T375 |
1 |
| others[2] |
224 |
1 |
|
T79 |
11 |
|
T88 |
16 |
|
T234 |
1 |
| others[3] |
345 |
1 |
|
T7 |
1 |
|
T79 |
14 |
|
T104 |
1 |
| false |
127 |
1 |
|
T79 |
3 |
|
T88 |
3 |
|
T31 |
1 |
| true |
5727 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T59 |
20 |
|
T60 |
1 |
|
T8 |
1 |
| others[1] |
1238 |
1 |
|
T59 |
25 |
|
T79 |
21 |
|
T44 |
1 |
| others[2] |
1238 |
1 |
|
T59 |
21 |
|
T72 |
1 |
|
T42 |
1 |
| others[3] |
2077 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
25 |
| false |
625 |
1 |
|
T6 |
1 |
|
T59 |
9 |
|
T79 |
8 |
| true |
435 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T59 |
23 |
|
T79 |
19 |
|
T88 |
16 |
| others[1] |
1271 |
1 |
|
T59 |
22 |
|
T8 |
1 |
|
T42 |
1 |
| others[2] |
1200 |
1 |
|
T16 |
1 |
|
T59 |
17 |
|
T79 |
25 |
| others[3] |
2093 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T59 |
32 |
| false |
622 |
1 |
|
T59 |
6 |
|
T60 |
1 |
|
T42 |
1 |
| true |
429 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T79 |
6 |
|
T88 |
5 |
|
T90 |
3 |
| others[1] |
115 |
1 |
|
T79 |
4 |
|
T88 |
3 |
|
T371 |
1 |
| others[2] |
89 |
1 |
|
T79 |
4 |
|
T88 |
6 |
|
T237 |
1 |
| others[3] |
166 |
1 |
|
T79 |
4 |
|
T88 |
6 |
|
T234 |
1 |
| false |
46 |
1 |
|
T16 |
1 |
|
T79 |
3 |
|
T88 |
1 |
| true |
6350 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T79 |
6 |
|
T88 |
11 |
|
T31 |
1 |
| others[1] |
222 |
1 |
|
T7 |
1 |
|
T79 |
10 |
|
T88 |
8 |
| others[2] |
222 |
1 |
|
T79 |
5 |
|
T88 |
9 |
|
T33 |
1 |
| others[3] |
374 |
1 |
|
T72 |
1 |
|
T20 |
1 |
|
T79 |
15 |
| false |
142 |
1 |
|
T227 |
1 |
|
T79 |
10 |
|
T88 |
9 |
| true |
5675 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T59 |
11 |
| others[1] |
1028 |
1 |
|
T59 |
4 |
|
T109 |
1 |
|
T42 |
1 |
| others[2] |
1075 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T59 |
11 |
| others[3] |
1758 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T59 |
14 |
| false |
564 |
1 |
|
T17 |
1 |
|
T59 |
7 |
|
T227 |
1 |
| true |
1408 |
1 |
|
T3 |
1 |
|
T59 |
53 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T79 |
10 |
|
T88 |
13 |
|
T197 |
1 |
| others[1] |
209 |
1 |
|
T79 |
6 |
|
T88 |
8 |
|
T256 |
1 |
| others[2] |
239 |
1 |
|
T79 |
13 |
|
T104 |
1 |
|
T88 |
11 |
| others[3] |
363 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T79 |
22 |
| false |
128 |
1 |
|
T79 |
2 |
|
T88 |
10 |
|
T90 |
3 |
| true |
5697 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T18 |
1 |
|
T79 |
12 |
|
T88 |
15 |
| others[1] |
218 |
1 |
|
T72 |
1 |
|
T79 |
4 |
|
T88 |
9 |
| others[2] |
209 |
1 |
|
T79 |
12 |
|
T88 |
12 |
|
T234 |
1 |
| others[3] |
362 |
1 |
|
T79 |
15 |
|
T88 |
18 |
|
T373 |
1 |
| false |
110 |
1 |
|
T79 |
4 |
|
T88 |
7 |
|
T225 |
1 |
| true |
5723 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1174 |
1 |
|
T6 |
1 |
|
T59 |
22 |
|
T8 |
1 |
| others[1] |
1230 |
1 |
|
T59 |
14 |
|
T60 |
1 |
|
T42 |
1 |
| others[2] |
1234 |
1 |
|
T59 |
17 |
|
T79 |
18 |
|
T44 |
1 |
| others[3] |
2127 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
| false |
671 |
1 |
|
T59 |
14 |
|
T79 |
9 |
|
T88 |
9 |
| true |
426 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |