Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T6 |
1 |
|
T59 |
13 |
|
T60 |
1 |
| others[1] |
1229 |
1 |
|
T59 |
21 |
|
T79 |
18 |
|
T88 |
15 |
| others[2] |
1209 |
1 |
|
T2 |
1 |
|
T59 |
22 |
|
T42 |
1 |
| others[3] |
2100 |
1 |
|
T16 |
1 |
|
T59 |
34 |
|
T42 |
1 |
| false |
673 |
1 |
|
T59 |
10 |
|
T42 |
1 |
|
T79 |
11 |
| true |
420 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T79 |
4 |
|
T88 |
3 |
|
T234 |
1 |
| others[1] |
103 |
1 |
|
T72 |
1 |
|
T79 |
2 |
|
T88 |
8 |
| others[2] |
115 |
1 |
|
T79 |
1 |
|
T88 |
5 |
|
T90 |
5 |
| others[3] |
195 |
1 |
|
T16 |
1 |
|
T79 |
3 |
|
T88 |
9 |
| false |
41 |
1 |
|
T79 |
3 |
|
T88 |
2 |
|
T371 |
1 |
| true |
6299 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T79 |
11 |
|
T88 |
12 |
|
T374 |
1 |
| others[1] |
253 |
1 |
|
T16 |
1 |
|
T79 |
10 |
|
T88 |
11 |
| others[2] |
249 |
1 |
|
T79 |
7 |
|
T88 |
11 |
|
T54 |
1 |
| others[3] |
397 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T227 |
1 |
| false |
126 |
1 |
|
T79 |
5 |
|
T88 |
5 |
|
T90 |
6 |
| true |
5619 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1140 |
1 |
|
T59 |
8 |
|
T60 |
1 |
|
T8 |
1 |
| others[1] |
1044 |
1 |
|
T59 |
10 |
|
T227 |
1 |
|
T42 |
1 |
| others[2] |
990 |
1 |
|
T59 |
5 |
|
T29 |
1 |
|
T79 |
14 |
| others[3] |
1765 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| false |
554 |
1 |
|
T6 |
1 |
|
T59 |
4 |
|
T79 |
10 |
| true |
1369 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T227 |
1 |
|
T79 |
8 |
|
T88 |
9 |
| others[1] |
233 |
1 |
|
T18 |
1 |
|
T79 |
13 |
|
T88 |
9 |
| others[2] |
240 |
1 |
|
T79 |
11 |
|
T88 |
12 |
|
T373 |
1 |
| others[3] |
383 |
1 |
|
T7 |
1 |
|
T72 |
1 |
|
T79 |
17 |
| false |
135 |
1 |
|
T79 |
6 |
|
T88 |
7 |
|
T31 |
1 |
| true |
5658 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T79 |
11 |
|
T88 |
10 |
|
T371 |
1 |
| others[1] |
214 |
1 |
|
T79 |
5 |
|
T88 |
13 |
|
T374 |
1 |
| others[2] |
247 |
1 |
|
T79 |
16 |
|
T88 |
14 |
|
T234 |
1 |
| others[3] |
362 |
1 |
|
T79 |
12 |
|
T88 |
13 |
|
T45 |
1 |
| false |
127 |
1 |
|
T79 |
6 |
|
T104 |
1 |
|
T88 |
6 |
| true |
5706 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T59 |
21 |
|
T60 |
1 |
|
T29 |
1 |
| others[1] |
1232 |
1 |
|
T2 |
1 |
|
T59 |
26 |
|
T42 |
2 |
| others[2] |
1226 |
1 |
|
T16 |
1 |
|
T59 |
18 |
|
T79 |
27 |
| others[3] |
2072 |
1 |
|
T59 |
25 |
|
T8 |
1 |
|
T42 |
1 |
| false |
677 |
1 |
|
T6 |
1 |
|
T59 |
10 |
|
T79 |
8 |
| true |
436 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T6 |
1 |
|
T59 |
21 |
|
T60 |
1 |
| others[1] |
1199 |
1 |
|
T59 |
15 |
|
T79 |
20 |
|
T88 |
16 |
| others[2] |
1296 |
1 |
|
T59 |
18 |
|
T42 |
1 |
|
T79 |
25 |
| others[3] |
2075 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T59 |
32 |
| false |
626 |
1 |
|
T2 |
1 |
|
T59 |
14 |
|
T42 |
1 |
| true |
424 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T79 |
5 |
|
T88 |
4 |
|
T90 |
3 |
| others[1] |
97 |
1 |
|
T79 |
2 |
|
T88 |
4 |
|
T90 |
3 |
| others[2] |
116 |
1 |
|
T79 |
4 |
|
T88 |
2 |
|
T237 |
1 |
| others[3] |
162 |
1 |
|
T16 |
1 |
|
T79 |
7 |
|
T88 |
5 |
| false |
67 |
1 |
|
T79 |
2 |
|
T88 |
3 |
|
T371 |
1 |
| true |
6312 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T79 |
13 |
|
T88 |
9 |
|
T225 |
1 |
| others[1] |
215 |
1 |
|
T16 |
1 |
|
T79 |
8 |
|
T88 |
9 |
| others[2] |
255 |
1 |
|
T72 |
1 |
|
T227 |
1 |
|
T79 |
11 |
| others[3] |
385 |
1 |
|
T3 |
1 |
|
T79 |
14 |
|
T88 |
16 |
| false |
134 |
1 |
|
T18 |
1 |
|
T79 |
3 |
|
T104 |
1 |
| true |
5668 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1071 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T59 |
10 |
| others[1] |
1091 |
1 |
|
T18 |
1 |
|
T59 |
6 |
|
T42 |
1 |
| others[2] |
1063 |
1 |
|
T59 |
15 |
|
T35 |
1 |
|
T20 |
1 |
| others[3] |
1731 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T7 |
1 |
| false |
500 |
1 |
|
T59 |
2 |
|
T8 |
1 |
|
T79 |
10 |
| true |
1406 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T59 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T79 |
7 |
|
T88 |
8 |
|
T256 |
1 |
| others[1] |
219 |
1 |
|
T79 |
8 |
|
T88 |
10 |
|
T125 |
1 |
| others[2] |
210 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T7 |
1 |
| others[3] |
393 |
1 |
|
T79 |
15 |
|
T88 |
21 |
|
T234 |
1 |
| false |
141 |
1 |
|
T79 |
9 |
|
T88 |
10 |
|
T90 |
6 |
| true |
5678 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T79 |
13 |
|
T88 |
11 |
|
T90 |
14 |
| others[1] |
193 |
1 |
|
T79 |
16 |
|
T88 |
11 |
|
T373 |
1 |
| others[2] |
233 |
1 |
|
T16 |
1 |
|
T227 |
1 |
|
T79 |
14 |
| others[3] |
394 |
1 |
|
T7 |
1 |
|
T18 |
1 |
|
T79 |
17 |
| false |
115 |
1 |
|
T79 |
1 |
|
T88 |
4 |
|
T256 |
1 |
| true |
5711 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T59 |
22 |
| others[1] |
1267 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
24 |
| others[2] |
1177 |
1 |
|
T59 |
16 |
|
T79 |
23 |
|
T44 |
1 |
| others[3] |
2054 |
1 |
|
T59 |
30 |
|
T12 |
1 |
|
T8 |
1 |
| false |
663 |
1 |
|
T59 |
8 |
|
T60 |
1 |
|
T42 |
1 |
| true |
444 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T59 |
24 |
|
T29 |
1 |
|
T79 |
20 |
| others[1] |
1281 |
1 |
|
T6 |
1 |
|
T59 |
22 |
|
T79 |
20 |
| others[2] |
1181 |
1 |
|
T59 |
21 |
|
T42 |
1 |
|
T79 |
21 |
| others[3] |
2062 |
1 |
|
T16 |
1 |
|
T59 |
25 |
|
T60 |
1 |
| false |
691 |
1 |
|
T2 |
1 |
|
T59 |
8 |
|
T79 |
7 |
| true |
426 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T79 |
1 |
|
T88 |
1 |
|
T256 |
1 |
| others[1] |
94 |
1 |
|
T79 |
6 |
|
T88 |
4 |
|
T237 |
1 |
| others[2] |
103 |
1 |
|
T79 |
4 |
|
T88 |
4 |
|
T234 |
1 |
| others[3] |
202 |
1 |
|
T79 |
7 |
|
T88 |
9 |
|
T55 |
1 |
| false |
48 |
1 |
|
T79 |
3 |
|
T90 |
2 |
|
T91 |
1 |
| true |
6310 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T79 |
6 |
|
T88 |
17 |
|
T374 |
1 |
| others[1] |
258 |
1 |
|
T79 |
6 |
|
T88 |
9 |
|
T237 |
1 |
| others[2] |
253 |
1 |
|
T18 |
1 |
|
T79 |
18 |
|
T88 |
12 |
| others[3] |
392 |
1 |
|
T4 |
1 |
|
T79 |
17 |
|
T88 |
8 |
| false |
130 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T61 |
1 |
| true |
5578 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T59 |
8 |
|
T8 |
1 |
|
T35 |
1 |
| others[1] |
1020 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
10 |
| others[2] |
1019 |
1 |
|
T17 |
1 |
|
T59 |
7 |
|
T60 |
1 |
| others[3] |
1795 |
1 |
|
T3 |
1 |
|
T59 |
20 |
|
T72 |
1 |
| false |
568 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T59 |
5 |
| true |
1420 |
1 |
|
T7 |
1 |
|
T18 |
1 |
|
T59 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T79 |
14 |
|
T88 |
11 |
|
T376 |
1 |
| others[1] |
237 |
1 |
|
T16 |
1 |
|
T72 |
1 |
|
T227 |
1 |
| others[2] |
231 |
1 |
|
T79 |
12 |
|
T88 |
17 |
|
T197 |
1 |
| others[3] |
369 |
1 |
|
T18 |
1 |
|
T79 |
16 |
|
T88 |
9 |
| false |
121 |
1 |
|
T17 |
1 |
|
T79 |
4 |
|
T88 |
3 |
| true |
5667 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T79 |
9 |
|
T88 |
8 |
|
T234 |
1 |
| others[1] |
217 |
1 |
|
T79 |
6 |
|
T88 |
12 |
|
T31 |
1 |
| others[2] |
203 |
1 |
|
T79 |
7 |
|
T88 |
8 |
|
T375 |
1 |
| others[3] |
375 |
1 |
|
T72 |
1 |
|
T79 |
20 |
|
T88 |
15 |
| false |
133 |
1 |
|
T18 |
1 |
|
T79 |
7 |
|
T88 |
8 |
| true |
5726 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T16 |
1 |
|
T59 |
12 |
|
T79 |
23 |
| others[1] |
1189 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T59 |
17 |
| others[2] |
1254 |
1 |
|
T6 |
1 |
|
T59 |
20 |
|
T8 |
1 |
| others[3] |
2061 |
1 |
|
T3 |
1 |
|
T59 |
43 |
|
T60 |
1 |
| false |
688 |
1 |
|
T59 |
8 |
|
T79 |
14 |
|
T88 |
10 |
| true |
435 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1288 |
1 |
|
T6 |
1 |
|
T59 |
23 |
|
T60 |
1 |
| others[1] |
1260 |
1 |
|
T2 |
1 |
|
T59 |
10 |
|
T42 |
1 |
| others[2] |
1224 |
1 |
|
T59 |
14 |
|
T8 |
1 |
|
T42 |
1 |
| others[3] |
2043 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T59 |
34 |
| false |
632 |
1 |
|
T59 |
19 |
|
T79 |
10 |
|
T88 |
7 |
| true |
415 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T79 |
3 |
|
T88 |
1 |
|
T234 |
1 |
| others[1] |
98 |
1 |
|
T79 |
5 |
|
T88 |
2 |
|
T90 |
4 |
| others[2] |
118 |
1 |
|
T79 |
1 |
|
T104 |
1 |
|
T88 |
2 |
| others[3] |
183 |
1 |
|
T16 |
1 |
|
T79 |
11 |
|
T88 |
9 |
| false |
60 |
1 |
|
T79 |
1 |
|
T88 |
3 |
|
T90 |
1 |
| true |
6291 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T79 |
13 |
|
T88 |
13 |
|
T234 |
1 |
| others[1] |
233 |
1 |
|
T72 |
1 |
|
T20 |
1 |
|
T79 |
11 |
| others[2] |
235 |
1 |
|
T7 |
1 |
|
T79 |
13 |
|
T88 |
8 |
| others[3] |
380 |
1 |
|
T16 |
1 |
|
T79 |
10 |
|
T88 |
10 |
| false |
143 |
1 |
|
T227 |
1 |
|
T79 |
8 |
|
T88 |
9 |
| true |
5654 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T59 |
9 |
|
T60 |
1 |
|
T72 |
1 |
| others[1] |
1005 |
1 |
|
T59 |
15 |
|
T8 |
1 |
|
T35 |
1 |
| others[2] |
1088 |
1 |
|
T17 |
1 |
|
T59 |
13 |
|
T42 |
1 |
| others[3] |
1813 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T59 |
15 |
| false |
548 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T59 |
8 |
| true |
1346 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T16 |
1 |
|
T79 |
9 |
|
T88 |
8 |
| others[1] |
246 |
1 |
|
T4 |
1 |
|
T72 |
1 |
|
T79 |
10 |
| others[2] |
225 |
1 |
|
T79 |
11 |
|
T88 |
4 |
|
T373 |
1 |
| others[3] |
399 |
1 |
|
T17 |
1 |
|
T7 |
1 |
|
T79 |
15 |
| false |
108 |
1 |
|
T79 |
5 |
|
T88 |
5 |
|
T78 |
1 |
| true |
5638 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T72 |
1 |
|
T79 |
6 |
|
T88 |
6 |
| others[1] |
240 |
1 |
|
T79 |
13 |
|
T104 |
1 |
|
T88 |
15 |
| others[2] |
229 |
1 |
|
T79 |
12 |
|
T88 |
10 |
|
T55 |
1 |
| others[3] |
347 |
1 |
|
T79 |
14 |
|
T88 |
15 |
|
T90 |
14 |
| false |
113 |
1 |
|
T18 |
1 |
|
T227 |
1 |
|
T79 |
5 |
| true |
5719 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T6 |
1 |
|
T59 |
18 |
|
T79 |
20 |
| others[1] |
1221 |
1 |
|
T59 |
18 |
|
T42 |
1 |
|
T79 |
16 |
| others[2] |
1219 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T59 |
22 |
| others[3] |
2122 |
1 |
|
T59 |
34 |
|
T60 |
1 |
|
T8 |
1 |
| false |
626 |
1 |
|
T2 |
1 |
|
T59 |
8 |
|
T79 |
6 |
| true |
429 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1172 |
1 |
|
T59 |
14 |
|
T42 |
1 |
|
T79 |
21 |
| others[1] |
1227 |
1 |
|
T59 |
21 |
|
T60 |
1 |
|
T109 |
1 |
| others[2] |
1294 |
1 |
|
T59 |
23 |
|
T79 |
20 |
|
T88 |
17 |
| others[3] |
2095 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| false |
650 |
1 |
|
T59 |
7 |
|
T79 |
14 |
|
T88 |
11 |
| true |
424 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T16 |
1 |
|
T79 |
9 |
|
T88 |
6 |
| others[1] |
113 |
1 |
|
T79 |
8 |
|
T88 |
7 |
|
T90 |
2 |
| others[2] |
78 |
1 |
|
T79 |
4 |
|
T88 |
1 |
|
T234 |
1 |
| others[3] |
173 |
1 |
|
T72 |
1 |
|
T79 |
3 |
|
T88 |
10 |
| false |
68 |
1 |
|
T79 |
3 |
|
T88 |
1 |
|
T125 |
1 |
| true |
6325 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T227 |
1 |
|
T79 |
12 |
|
T88 |
11 |
| others[1] |
247 |
1 |
|
T79 |
9 |
|
T88 |
9 |
|
T234 |
1 |
| others[2] |
213 |
1 |
|
T4 |
1 |
|
T61 |
1 |
|
T79 |
8 |
| others[3] |
368 |
1 |
|
T18 |
1 |
|
T79 |
24 |
|
T88 |
14 |
| false |
137 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T79 |
4 |
| true |
5649 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |