Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T3 |
1 |
|
T59 |
9 |
|
T42 |
2 |
| others[1] |
1047 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| others[2] |
1038 |
1 |
|
T59 |
10 |
|
T72 |
1 |
|
T79 |
22 |
| others[3] |
1792 |
1 |
|
T16 |
1 |
|
T59 |
21 |
|
T29 |
1 |
| false |
533 |
1 |
|
T6 |
1 |
|
T59 |
4 |
|
T42 |
1 |
| true |
1391 |
1 |
|
T7 |
1 |
|
T18 |
1 |
|
T59 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T79 |
21 |
|
T104 |
1 |
|
T88 |
10 |
| others[1] |
204 |
1 |
|
T4 |
1 |
|
T79 |
6 |
|
T88 |
5 |
| others[2] |
230 |
1 |
|
T16 |
1 |
|
T227 |
1 |
|
T79 |
8 |
| others[3] |
399 |
1 |
|
T79 |
13 |
|
T88 |
16 |
|
T374 |
1 |
| false |
121 |
1 |
|
T79 |
2 |
|
T88 |
5 |
|
T56 |
1 |
| true |
5688 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T227 |
1 |
|
T79 |
12 |
|
T88 |
8 |
| others[1] |
233 |
1 |
|
T79 |
9 |
|
T88 |
10 |
|
T234 |
1 |
| others[2] |
222 |
1 |
|
T16 |
1 |
|
T79 |
9 |
|
T88 |
9 |
| others[3] |
366 |
1 |
|
T7 |
1 |
|
T79 |
8 |
|
T104 |
1 |
| false |
102 |
1 |
|
T79 |
7 |
|
T88 |
4 |
|
T371 |
1 |
| true |
5702 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T59 |
21 |
| others[1] |
1261 |
1 |
|
T59 |
19 |
|
T29 |
1 |
|
T79 |
23 |
| others[2] |
1240 |
1 |
|
T59 |
19 |
|
T42 |
1 |
|
T79 |
18 |
| others[3] |
2011 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
29 |
| false |
642 |
1 |
|
T59 |
12 |
|
T60 |
1 |
|
T79 |
13 |
| true |
435 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T59 |
15 |
|
T42 |
1 |
|
T79 |
17 |
| others[1] |
1220 |
1 |
|
T6 |
1 |
|
T59 |
21 |
|
T60 |
1 |
| others[2] |
1263 |
1 |
|
T59 |
18 |
|
T42 |
1 |
|
T29 |
1 |
| others[3] |
2117 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
| false |
657 |
1 |
|
T59 |
15 |
|
T79 |
14 |
|
T88 |
7 |
| true |
423 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T79 |
5 |
|
T88 |
3 |
|
T237 |
1 |
| others[1] |
110 |
1 |
|
T227 |
1 |
|
T79 |
7 |
|
T88 |
2 |
| others[2] |
94 |
1 |
|
T79 |
2 |
|
T88 |
2 |
|
T90 |
6 |
| others[3] |
165 |
1 |
|
T79 |
4 |
|
T88 |
3 |
|
T234 |
1 |
| false |
57 |
1 |
|
T79 |
5 |
|
T88 |
4 |
|
T371 |
1 |
| true |
6341 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T72 |
1 |
|
T61 |
1 |
|
T79 |
11 |
| others[1] |
258 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T79 |
14 |
| others[2] |
230 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T79 |
10 |
| others[3] |
387 |
1 |
|
T17 |
1 |
|
T79 |
20 |
|
T88 |
18 |
| false |
124 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T88 |
4 |
| true |
5614 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T59 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T6 |
1 |
|
T59 |
5 |
|
T12 |
1 |
| others[1] |
1063 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T59 |
14 |
| others[2] |
1043 |
1 |
|
T59 |
11 |
|
T227 |
1 |
|
T42 |
1 |
| others[3] |
1762 |
1 |
|
T2 |
1 |
|
T59 |
16 |
|
T109 |
1 |
| false |
577 |
1 |
|
T59 |
7 |
|
T8 |
1 |
|
T79 |
12 |
| true |
1351 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T79 |
5 |
|
T104 |
1 |
|
T88 |
7 |
| others[1] |
258 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T79 |
18 |
| others[2] |
223 |
1 |
|
T4 |
1 |
|
T79 |
9 |
|
T88 |
6 |
| others[3] |
405 |
1 |
|
T79 |
28 |
|
T88 |
17 |
|
T234 |
1 |
| false |
117 |
1 |
|
T79 |
5 |
|
T88 |
2 |
|
T256 |
1 |
| true |
5631 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T7 |
1 |
|
T79 |
14 |
|
T88 |
7 |
| others[1] |
241 |
1 |
|
T79 |
10 |
|
T88 |
16 |
|
T125 |
1 |
| others[2] |
219 |
1 |
|
T79 |
8 |
|
T88 |
4 |
|
T45 |
1 |
| others[3] |
383 |
1 |
|
T79 |
13 |
|
T88 |
18 |
|
T234 |
1 |
| false |
102 |
1 |
|
T227 |
1 |
|
T79 |
7 |
|
T88 |
4 |
| true |
5686 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1192 |
1 |
|
T6 |
1 |
|
T59 |
17 |
|
T79 |
16 |
| others[1] |
1223 |
1 |
|
T2 |
1 |
|
T59 |
21 |
|
T42 |
1 |
| others[2] |
1248 |
1 |
|
T59 |
15 |
|
T79 |
21 |
|
T104 |
1 |
| others[3] |
2085 |
1 |
|
T59 |
37 |
|
T60 |
1 |
|
T42 |
1 |
| false |
672 |
1 |
|
T16 |
1 |
|
T59 |
10 |
|
T8 |
1 |
| true |
442 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T59 |
20 |
|
T42 |
2 |
|
T79 |
13 |
| others[1] |
1251 |
1 |
|
T16 |
1 |
|
T59 |
19 |
|
T60 |
1 |
| others[2] |
1219 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T59 |
22 |
| others[3] |
2042 |
1 |
|
T59 |
30 |
|
T8 |
1 |
|
T109 |
1 |
| false |
672 |
1 |
|
T59 |
9 |
|
T79 |
8 |
|
T88 |
10 |
| true |
420 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T79 |
7 |
|
T88 |
3 |
|
T237 |
1 |
| others[1] |
107 |
1 |
|
T16 |
1 |
|
T72 |
1 |
|
T79 |
3 |
| others[2] |
112 |
1 |
|
T79 |
7 |
|
T88 |
2 |
|
T225 |
1 |
| others[3] |
155 |
1 |
|
T79 |
5 |
|
T88 |
5 |
|
T234 |
1 |
| false |
53 |
1 |
|
T79 |
3 |
|
T88 |
2 |
|
T371 |
1 |
| true |
6331 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T16 |
1 |
|
T79 |
10 |
|
T88 |
13 |
| others[1] |
224 |
1 |
|
T7 |
1 |
|
T72 |
1 |
|
T79 |
21 |
| others[2] |
242 |
1 |
|
T4 |
1 |
|
T61 |
1 |
|
T79 |
9 |
| others[3] |
424 |
1 |
|
T79 |
18 |
|
T104 |
1 |
|
T88 |
15 |
| false |
125 |
1 |
|
T227 |
1 |
|
T79 |
3 |
|
T88 |
5 |
| true |
5632 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T16 |
1 |
|
T59 |
11 |
|
T79 |
17 |
| others[1] |
1061 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| others[2] |
1149 |
1 |
|
T18 |
1 |
|
T59 |
8 |
|
T12 |
1 |
| others[3] |
1780 |
1 |
|
T6 |
1 |
|
T59 |
20 |
|
T60 |
1 |
| false |
487 |
1 |
|
T3 |
1 |
|
T59 |
5 |
|
T42 |
1 |
| true |
1356 |
1 |
|
T7 |
1 |
|
T59 |
43 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T4 |
1 |
|
T72 |
1 |
|
T79 |
11 |
| others[1] |
235 |
1 |
|
T79 |
10 |
|
T88 |
10 |
|
T32 |
1 |
| others[2] |
213 |
1 |
|
T17 |
1 |
|
T227 |
1 |
|
T79 |
9 |
| others[3] |
409 |
1 |
|
T7 |
1 |
|
T79 |
17 |
|
T104 |
1 |
| false |
110 |
1 |
|
T18 |
1 |
|
T79 |
6 |
|
T88 |
4 |
| true |
5660 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T79 |
8 |
|
T88 |
13 |
|
T234 |
1 |
| others[1] |
226 |
1 |
|
T79 |
13 |
|
T88 |
7 |
|
T371 |
1 |
| others[2] |
241 |
1 |
|
T16 |
1 |
|
T227 |
1 |
|
T79 |
15 |
| others[3] |
357 |
1 |
|
T79 |
17 |
|
T88 |
20 |
|
T32 |
1 |
| false |
123 |
1 |
|
T79 |
3 |
|
T88 |
7 |
|
T373 |
1 |
| true |
5718 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
17 |
| others[1] |
1272 |
1 |
|
T6 |
1 |
|
T59 |
22 |
|
T79 |
19 |
| others[2] |
1222 |
1 |
|
T18 |
1 |
|
T59 |
20 |
|
T29 |
1 |
| others[3] |
2089 |
1 |
|
T59 |
37 |
|
T60 |
1 |
|
T42 |
2 |
| false |
580 |
1 |
|
T59 |
4 |
|
T79 |
7 |
|
T88 |
14 |
| true |
433 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1214 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
18 |
| others[1] |
1287 |
1 |
|
T59 |
21 |
|
T8 |
1 |
|
T42 |
1 |
| others[2] |
1216 |
1 |
|
T6 |
1 |
|
T59 |
18 |
|
T29 |
1 |
| others[3] |
2070 |
1 |
|
T59 |
34 |
|
T60 |
1 |
|
T79 |
22 |
| false |
649 |
1 |
|
T59 |
9 |
|
T79 |
12 |
|
T88 |
9 |
| true |
426 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T16 |
1 |
|
T79 |
2 |
|
T88 |
8 |
| others[1] |
103 |
1 |
|
T79 |
8 |
|
T88 |
4 |
|
T31 |
1 |
| others[2] |
109 |
1 |
|
T72 |
1 |
|
T79 |
1 |
|
T88 |
5 |
| others[3] |
158 |
1 |
|
T79 |
7 |
|
T88 |
4 |
|
T234 |
1 |
| false |
58 |
1 |
|
T79 |
1 |
|
T88 |
4 |
|
T45 |
1 |
| true |
6314 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T61 |
1 |
|
T79 |
6 |
|
T88 |
11 |
| others[1] |
254 |
1 |
|
T20 |
1 |
|
T79 |
13 |
|
T88 |
8 |
| others[2] |
249 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T72 |
1 |
| others[3] |
404 |
1 |
|
T18 |
1 |
|
T79 |
20 |
|
T88 |
19 |
| false |
111 |
1 |
|
T79 |
4 |
|
T88 |
3 |
|
T90 |
2 |
| true |
5627 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T59 |
4 |
|
T35 |
1 |
|
T29 |
1 |
| others[1] |
1062 |
1 |
|
T59 |
9 |
|
T42 |
1 |
|
T61 |
1 |
| others[2] |
1079 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T59 |
15 |
| others[3] |
1734 |
1 |
|
T2 |
1 |
|
T59 |
19 |
|
T109 |
1 |
| false |
553 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T59 |
6 |
| true |
1395 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T72 |
1 |
|
T79 |
11 |
|
T88 |
10 |
| others[1] |
242 |
1 |
|
T79 |
15 |
|
T88 |
7 |
|
T90 |
11 |
| others[2] |
226 |
1 |
|
T79 |
4 |
|
T88 |
10 |
|
T55 |
1 |
| others[3] |
360 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| false |
115 |
1 |
|
T79 |
5 |
|
T88 |
1 |
|
T376 |
1 |
| true |
5679 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T227 |
1 |
|
T79 |
12 |
|
T88 |
14 |
| others[1] |
224 |
1 |
|
T79 |
15 |
|
T104 |
1 |
|
T88 |
7 |
| others[2] |
223 |
1 |
|
T7 |
1 |
|
T79 |
12 |
|
T88 |
12 |
| others[3] |
351 |
1 |
|
T79 |
14 |
|
T88 |
19 |
|
T234 |
1 |
| false |
101 |
1 |
|
T79 |
6 |
|
T237 |
1 |
|
T90 |
13 |
| true |
5748 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1232 |
1 |
|
T16 |
1 |
|
T59 |
23 |
|
T29 |
1 |
| others[1] |
1232 |
1 |
|
T6 |
1 |
|
T59 |
14 |
|
T60 |
1 |
| others[2] |
1259 |
1 |
|
T59 |
20 |
|
T42 |
1 |
|
T79 |
20 |
| others[3] |
2074 |
1 |
|
T59 |
36 |
|
T12 |
1 |
|
T8 |
1 |
| false |
628 |
1 |
|
T2 |
1 |
|
T59 |
7 |
|
T42 |
1 |
| true |
437 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T6 |
1 |
|
T59 |
24 |
|
T79 |
23 |
| others[1] |
1197 |
1 |
|
T59 |
23 |
|
T42 |
1 |
|
T79 |
13 |
| others[2] |
1243 |
1 |
|
T59 |
20 |
|
T60 |
1 |
|
T79 |
27 |
| others[3] |
2069 |
1 |
|
T16 |
1 |
|
T59 |
26 |
|
T42 |
1 |
| false |
656 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T59 |
7 |
| true |
429 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T79 |
4 |
|
T88 |
5 |
|
T234 |
1 |
| others[1] |
111 |
1 |
|
T79 |
2 |
|
T88 |
4 |
|
T90 |
5 |
| others[2] |
99 |
1 |
|
T18 |
1 |
|
T79 |
6 |
|
T88 |
5 |
| others[3] |
159 |
1 |
|
T79 |
5 |
|
T88 |
6 |
|
T55 |
1 |
| false |
67 |
1 |
|
T371 |
1 |
|
T90 |
3 |
|
T377 |
1 |
| true |
6334 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T4 |
1 |
|
T79 |
13 |
|
T88 |
17 |
| others[1] |
232 |
1 |
|
T7 |
1 |
|
T79 |
8 |
|
T88 |
5 |
| others[2] |
223 |
1 |
|
T79 |
7 |
|
T88 |
9 |
|
T27 |
1 |
| others[3] |
392 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T79 |
22 |
| false |
125 |
1 |
|
T79 |
5 |
|
T104 |
1 |
|
T88 |
10 |
| true |
5640 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T59 |
8 |
|
T60 |
1 |
|
T35 |
1 |
| others[1] |
1008 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[2] |
1086 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T59 |
14 |
| others[3] |
1765 |
1 |
|
T17 |
1 |
|
T59 |
17 |
|
T42 |
2 |
| false |
573 |
1 |
|
T59 |
3 |
|
T8 |
1 |
|
T79 |
11 |
| true |
1367 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T59 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T16 |
1 |
|
T79 |
3 |
|
T88 |
10 |
| others[1] |
228 |
1 |
|
T79 |
13 |
|
T88 |
7 |
|
T197 |
1 |
| others[2] |
224 |
1 |
|
T79 |
11 |
|
T88 |
9 |
|
T54 |
1 |
| others[3] |
395 |
1 |
|
T79 |
21 |
|
T88 |
14 |
|
T237 |
1 |
| false |
110 |
1 |
|
T79 |
5 |
|
T88 |
6 |
|
T234 |
1 |
| true |
5697 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T79 |
7 |
|
T88 |
10 |
|
T55 |
1 |
| others[1] |
217 |
1 |
|
T18 |
1 |
|
T79 |
6 |
|
T88 |
9 |
| others[2] |
233 |
1 |
|
T79 |
15 |
|
T88 |
12 |
|
T32 |
1 |
| others[3] |
344 |
1 |
|
T16 |
1 |
|
T79 |
12 |
|
T88 |
17 |
| false |
112 |
1 |
|
T79 |
5 |
|
T104 |
1 |
|
T88 |
7 |
| true |
5733 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |