Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T59 |
16 |
| others[1] |
1276 |
1 |
|
T59 |
27 |
|
T60 |
1 |
|
T35 |
1 |
| others[2] |
1217 |
1 |
|
T2 |
1 |
|
T59 |
17 |
|
T42 |
1 |
| others[3] |
2113 |
1 |
|
T59 |
34 |
|
T8 |
1 |
|
T42 |
1 |
| false |
597 |
1 |
|
T59 |
6 |
|
T42 |
1 |
|
T79 |
12 |
| true |
428 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T59 |
23 |
|
T79 |
13 |
|
T88 |
26 |
| others[1] |
1228 |
1 |
|
T6 |
1 |
|
T59 |
18 |
|
T29 |
1 |
| others[2] |
1216 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| others[3] |
2121 |
1 |
|
T59 |
27 |
|
T60 |
1 |
|
T8 |
1 |
| false |
662 |
1 |
|
T59 |
8 |
|
T42 |
1 |
|
T79 |
9 |
| true |
416 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T16 |
1 |
|
T79 |
6 |
|
T88 |
6 |
| others[1] |
112 |
1 |
|
T79 |
1 |
|
T88 |
6 |
|
T373 |
1 |
| others[2] |
112 |
1 |
|
T18 |
1 |
|
T79 |
6 |
|
T88 |
1 |
| others[3] |
157 |
1 |
|
T79 |
6 |
|
T88 |
5 |
|
T234 |
1 |
| false |
52 |
1 |
|
T72 |
1 |
|
T79 |
2 |
|
T88 |
2 |
| true |
6318 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T79 |
13 |
|
T88 |
8 |
|
T30 |
1 |
| others[1] |
217 |
1 |
|
T79 |
10 |
|
T88 |
8 |
|
T56 |
1 |
| others[2] |
226 |
1 |
|
T4 |
1 |
|
T79 |
11 |
|
T88 |
8 |
| others[3] |
404 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T61 |
1 |
| false |
102 |
1 |
|
T79 |
6 |
|
T88 |
4 |
|
T45 |
1 |
| true |
5673 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1060 |
1 |
|
T18 |
1 |
|
T59 |
8 |
|
T35 |
1 |
| others[1] |
1096 |
1 |
|
T7 |
1 |
|
T59 |
13 |
|
T20 |
1 |
| others[2] |
1029 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T59 |
9 |
| others[3] |
1769 |
1 |
|
T6 |
1 |
|
T59 |
16 |
|
T60 |
1 |
| false |
535 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T59 |
2 |
| true |
1373 |
1 |
|
T17 |
1 |
|
T59 |
52 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T79 |
12 |
| others[1] |
233 |
1 |
|
T16 |
1 |
|
T79 |
4 |
|
T88 |
14 |
| others[2] |
242 |
1 |
|
T79 |
10 |
|
T88 |
12 |
|
T376 |
1 |
| others[3] |
372 |
1 |
|
T79 |
12 |
|
T104 |
1 |
|
T88 |
20 |
| false |
101 |
1 |
|
T79 |
5 |
|
T88 |
4 |
|
T90 |
4 |
| true |
5676 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T16 |
1 |
|
T79 |
7 |
|
T88 |
7 |
| others[1] |
216 |
1 |
|
T79 |
18 |
|
T88 |
10 |
|
T125 |
1 |
| others[2] |
222 |
1 |
|
T79 |
12 |
|
T88 |
7 |
|
T375 |
1 |
| others[3] |
378 |
1 |
|
T72 |
1 |
|
T79 |
17 |
|
T88 |
14 |
| false |
121 |
1 |
|
T79 |
4 |
|
T88 |
8 |
|
T234 |
1 |
| true |
5699 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T59 |
24 |
|
T42 |
1 |
|
T79 |
23 |
| others[1] |
1240 |
1 |
|
T6 |
1 |
|
T59 |
18 |
|
T42 |
1 |
| others[2] |
1261 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
24 |
| others[3] |
2045 |
1 |
|
T59 |
25 |
|
T60 |
1 |
|
T8 |
1 |
| false |
637 |
1 |
|
T59 |
9 |
|
T12 |
1 |
|
T79 |
4 |
| true |
420 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T2 |
1 |
|
T59 |
22 |
|
T42 |
1 |
| others[1] |
1228 |
1 |
|
T59 |
19 |
|
T29 |
1 |
|
T79 |
18 |
| others[2] |
1242 |
1 |
|
T16 |
1 |
|
T59 |
11 |
|
T79 |
20 |
| others[3] |
2109 |
1 |
|
T6 |
1 |
|
T59 |
34 |
|
T60 |
1 |
| false |
662 |
1 |
|
T59 |
14 |
|
T79 |
8 |
|
T88 |
7 |
| true |
415 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T79 |
2 |
|
T88 |
2 |
|
T90 |
3 |
| others[1] |
105 |
1 |
|
T79 |
3 |
|
T88 |
6 |
|
T237 |
1 |
| others[2] |
118 |
1 |
|
T79 |
6 |
|
T88 |
6 |
|
T371 |
1 |
| others[3] |
149 |
1 |
|
T79 |
6 |
|
T88 |
7 |
|
T234 |
1 |
| false |
54 |
1 |
|
T79 |
1 |
|
T88 |
1 |
|
T90 |
2 |
| true |
6349 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T16 |
1 |
|
T79 |
3 |
|
T88 |
9 |
| others[1] |
234 |
1 |
|
T18 |
1 |
|
T79 |
4 |
|
T88 |
8 |
| others[2] |
247 |
1 |
|
T3 |
1 |
|
T72 |
1 |
|
T61 |
1 |
| others[3] |
388 |
1 |
|
T4 |
1 |
|
T79 |
17 |
|
T88 |
16 |
| false |
111 |
1 |
|
T17 |
1 |
|
T79 |
8 |
|
T88 |
5 |
| true |
5640 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1091 |
1 |
|
T59 |
12 |
|
T60 |
1 |
|
T29 |
1 |
| others[1] |
986 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T59 |
11 |
| others[2] |
1060 |
1 |
|
T59 |
10 |
|
T42 |
2 |
|
T79 |
20 |
| others[3] |
1773 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T59 |
11 |
| false |
584 |
1 |
|
T6 |
1 |
|
T59 |
4 |
|
T8 |
1 |
| true |
1368 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T79 |
12 |
|
T88 |
10 |
|
T90 |
9 |
| others[1] |
218 |
1 |
|
T79 |
9 |
|
T88 |
4 |
|
T373 |
1 |
| others[2] |
244 |
1 |
|
T79 |
11 |
|
T88 |
10 |
|
T78 |
1 |
| others[3] |
378 |
1 |
|
T7 |
1 |
|
T227 |
1 |
|
T79 |
12 |
| false |
116 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T79 |
5 |
| true |
5686 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T18 |
1 |
|
T79 |
11 |
|
T88 |
9 |
| others[1] |
250 |
1 |
|
T79 |
9 |
|
T88 |
19 |
|
T373 |
1 |
| others[2] |
218 |
1 |
|
T7 |
1 |
|
T79 |
6 |
|
T104 |
1 |
| others[3] |
337 |
1 |
|
T72 |
1 |
|
T79 |
18 |
|
T88 |
11 |
| false |
108 |
1 |
|
T79 |
4 |
|
T88 |
6 |
|
T256 |
1 |
| true |
5721 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T6 |
1 |
|
T59 |
22 |
|
T79 |
15 |
| others[1] |
1213 |
1 |
|
T59 |
13 |
|
T8 |
1 |
|
T79 |
20 |
| others[2] |
1214 |
1 |
|
T16 |
1 |
|
T59 |
16 |
|
T109 |
1 |
| others[3] |
2050 |
1 |
|
T2 |
1 |
|
T59 |
40 |
|
T60 |
1 |
| false |
683 |
1 |
|
T59 |
9 |
|
T12 |
1 |
|
T79 |
10 |
| true |
440 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T59 |
15 |
|
T79 |
18 |
|
T44 |
1 |
| others[1] |
1290 |
1 |
|
T59 |
24 |
|
T60 |
1 |
|
T42 |
2 |
| others[2] |
1213 |
1 |
|
T59 |
21 |
|
T29 |
1 |
|
T79 |
19 |
| others[3] |
1997 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| false |
699 |
1 |
|
T59 |
13 |
|
T8 |
1 |
|
T79 |
13 |
| true |
421 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T79 |
5 |
|
T88 |
6 |
|
T90 |
2 |
| others[1] |
110 |
1 |
|
T79 |
3 |
|
T88 |
5 |
|
T234 |
1 |
| others[2] |
99 |
1 |
|
T79 |
5 |
|
T88 |
5 |
|
T225 |
1 |
| others[3] |
195 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T79 |
5 |
| false |
59 |
1 |
|
T79 |
2 |
|
T88 |
2 |
|
T371 |
1 |
| true |
6304 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T79 |
15 |
|
T88 |
11 |
|
T90 |
5 |
| others[1] |
246 |
1 |
|
T18 |
1 |
|
T79 |
7 |
|
T88 |
11 |
| others[2] |
223 |
1 |
|
T7 |
1 |
|
T61 |
1 |
|
T79 |
9 |
| others[3] |
373 |
1 |
|
T227 |
1 |
|
T79 |
9 |
|
T88 |
19 |
| false |
133 |
1 |
|
T79 |
11 |
|
T88 |
3 |
|
T54 |
1 |
| true |
5660 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T59 |
3 |
| others[1] |
1054 |
1 |
|
T2 |
1 |
|
T59 |
9 |
|
T79 |
11 |
| others[2] |
1079 |
1 |
|
T59 |
12 |
|
T12 |
1 |
|
T79 |
22 |
| others[3] |
1731 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T59 |
20 |
| false |
547 |
1 |
|
T18 |
1 |
|
T59 |
5 |
|
T79 |
15 |
| true |
1393 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T59 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T79 |
8 |
|
T88 |
14 |
|
T371 |
2 |
| others[1] |
214 |
1 |
|
T16 |
1 |
|
T79 |
11 |
|
T88 |
4 |
| others[2] |
243 |
1 |
|
T7 |
1 |
|
T79 |
6 |
|
T88 |
10 |
| others[3] |
385 |
1 |
|
T72 |
1 |
|
T79 |
13 |
|
T88 |
18 |
| false |
107 |
1 |
|
T79 |
8 |
|
T88 |
5 |
|
T32 |
1 |
| true |
5672 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T79 |
9 |
|
T88 |
5 |
|
T256 |
1 |
| others[1] |
224 |
1 |
|
T16 |
1 |
|
T79 |
10 |
|
T104 |
1 |
| others[2] |
189 |
1 |
|
T227 |
1 |
|
T79 |
6 |
|
T88 |
7 |
| others[3] |
390 |
1 |
|
T79 |
17 |
|
T88 |
22 |
|
T234 |
1 |
| false |
121 |
1 |
|
T79 |
5 |
|
T88 |
2 |
|
T371 |
1 |
| true |
5717 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T59 |
20 |
|
T60 |
1 |
|
T79 |
14 |
| others[1] |
1175 |
1 |
|
T16 |
1 |
|
T59 |
20 |
|
T12 |
1 |
| others[2] |
1278 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
| others[3] |
2106 |
1 |
|
T59 |
32 |
|
T8 |
1 |
|
T42 |
1 |
| false |
621 |
1 |
|
T59 |
9 |
|
T42 |
2 |
|
T79 |
11 |
| true |
445 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T59 |
26 |
|
T42 |
2 |
|
T79 |
15 |
| others[1] |
1281 |
1 |
|
T6 |
1 |
|
T59 |
13 |
|
T60 |
1 |
| others[2] |
1260 |
1 |
|
T16 |
1 |
|
T59 |
15 |
|
T29 |
1 |
| others[3] |
2034 |
1 |
|
T2 |
1 |
|
T59 |
32 |
|
T8 |
1 |
| false |
600 |
1 |
|
T59 |
14 |
|
T79 |
11 |
|
T44 |
1 |
| true |
426 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T79 |
3 |
|
T88 |
7 |
|
T225 |
1 |
| others[1] |
84 |
1 |
|
T79 |
4 |
|
T88 |
2 |
|
T90 |
1 |
| others[2] |
109 |
1 |
|
T79 |
4 |
|
T88 |
6 |
|
T234 |
1 |
| others[3] |
168 |
1 |
|
T79 |
7 |
|
T88 |
2 |
|
T371 |
1 |
| false |
55 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T79 |
1 |
| true |
6340 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T20 |
1 |
|
T79 |
9 |
|
T88 |
8 |
| others[1] |
234 |
1 |
|
T79 |
12 |
|
T88 |
8 |
|
T237 |
1 |
| others[2] |
228 |
1 |
|
T4 |
1 |
|
T79 |
9 |
|
T88 |
10 |
| others[3] |
408 |
1 |
|
T7 |
1 |
|
T72 |
1 |
|
T227 |
1 |
| false |
126 |
1 |
|
T79 |
12 |
|
T88 |
5 |
|
T34 |
1 |
| true |
5612 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1028 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T59 |
10 |
| others[1] |
1048 |
1 |
|
T3 |
1 |
|
T59 |
10 |
|
T12 |
1 |
| others[2] |
1042 |
1 |
|
T59 |
12 |
|
T35 |
1 |
|
T79 |
22 |
| others[3] |
1762 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T18 |
1 |
| false |
564 |
1 |
|
T59 |
5 |
|
T79 |
19 |
|
T88 |
10 |
| true |
1418 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T59 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T4 |
1 |
|
T79 |
12 |
|
T88 |
12 |
| others[1] |
253 |
1 |
|
T79 |
10 |
|
T104 |
1 |
|
T88 |
9 |
| others[2] |
227 |
1 |
|
T16 |
1 |
|
T79 |
9 |
|
T88 |
8 |
| others[3] |
385 |
1 |
|
T79 |
14 |
|
T88 |
22 |
|
T197 |
1 |
| false |
127 |
1 |
|
T79 |
9 |
|
T88 |
4 |
|
T90 |
6 |
| true |
5644 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T79 |
6 |
|
T88 |
10 |
|
T45 |
1 |
| others[1] |
212 |
1 |
|
T16 |
1 |
|
T79 |
13 |
|
T88 |
11 |
| others[2] |
252 |
1 |
|
T227 |
1 |
|
T79 |
10 |
|
T88 |
10 |
| others[3] |
363 |
1 |
|
T79 |
15 |
|
T104 |
1 |
|
T88 |
16 |
| false |
90 |
1 |
|
T79 |
4 |
|
T88 |
6 |
|
T371 |
1 |
| true |
5721 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1297 |
1 |
|
T16 |
1 |
|
T59 |
20 |
|
T60 |
1 |
| others[1] |
1276 |
1 |
|
T59 |
18 |
|
T79 |
24 |
|
T88 |
25 |
| others[2] |
1225 |
1 |
|
T2 |
1 |
|
T59 |
16 |
|
T42 |
1 |
| others[3] |
2047 |
1 |
|
T59 |
37 |
|
T79 |
34 |
|
T44 |
1 |
| false |
593 |
1 |
|
T6 |
1 |
|
T59 |
9 |
|
T42 |
1 |
| true |
424 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T378 |
1 |
|
T379 |
1 |
|
T380 |
1 |
| others[1] |
11 |
1 |
|
T83 |
1 |
|
T145 |
1 |
|
T243 |
1 |
| others[2] |
4 |
1 |
|
T381 |
1 |
|
T382 |
1 |
|
T383 |
1 |
| others[3] |
14 |
1 |
|
T35 |
1 |
|
T38 |
1 |
|
T384 |
1 |
| false |
7 |
1 |
|
T385 |
1 |
|
T386 |
1 |
|
T387 |
1 |
| true |
38 |
1 |
|
T13 |
1 |
|
T82 |
2 |
|
T124 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T105 |
1 |
|
T244 |
1 |
|
T388 |
1 |
| others[1] |
2 |
1 |
|
T235 |
1 |
|
T389 |
1 |
|
- |
- |
| others[2] |
5 |
1 |
|
T390 |
1 |
|
T391 |
1 |
|
T392 |
1 |
| others[3] |
6 |
1 |
|
T24 |
1 |
|
T393 |
1 |
|
T394 |
1 |
| false |
5 |
1 |
|
T395 |
1 |
|
T396 |
1 |
|
T368 |
1 |
| true |
25 |
1 |
|
T1 |
1 |
|
T99 |
1 |
|
T359 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |