Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10582 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
772 |
1 |
|
T16 |
1 |
|
T42 |
1 |
|
T79 |
16 |
| others[2] |
824 |
1 |
|
T60 |
1 |
|
T79 |
16 |
|
T88 |
15 |
| others[3] |
1306 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T8 |
1 |
| false |
416 |
1 |
|
T42 |
1 |
|
T79 |
12 |
|
T88 |
8 |
| true |
500 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2561 |
1 |
|
T6 |
1 |
|
T59 |
21 |
|
T46 |
12 |
| others[1] |
2500 |
1 |
|
T59 |
18 |
|
T60 |
1 |
|
T46 |
3 |
| others[2] |
2434 |
1 |
|
T18 |
1 |
|
T59 |
22 |
|
T13 |
1 |
| others[3] |
4086 |
1 |
|
T2 |
1 |
|
T59 |
32 |
|
T13 |
1 |
| false |
1252 |
1 |
|
T59 |
7 |
|
T46 |
4 |
|
T79 |
9 |
| true |
1567 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10017 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| others[1] |
267 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T61 |
1 |
| others[2] |
280 |
1 |
|
T79 |
6 |
|
T88 |
14 |
|
T375 |
1 |
| others[3] |
484 |
1 |
|
T6 |
1 |
|
T20 |
1 |
|
T79 |
20 |
| false |
130 |
1 |
|
T29 |
1 |
|
T79 |
5 |
|
T88 |
2 |
| true |
3222 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10221 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
466 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T79 |
10 |
| others[2] |
500 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T61 |
1 |
| others[3] |
738 |
1 |
|
T4 |
1 |
|
T35 |
1 |
|
T79 |
14 |
| false |
227 |
1 |
|
T79 |
4 |
|
T88 |
5 |
|
T19 |
1 |
| true |
2248 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10022 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T59 |
100 |
| others[1] |
250 |
1 |
|
T6 |
1 |
|
T79 |
9 |
|
T44 |
1 |
| others[2] |
249 |
1 |
|
T79 |
9 |
|
T88 |
13 |
|
T73 |
1 |
| others[3] |
426 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T8 |
1 |
| false |
135 |
1 |
|
T72 |
1 |
|
T79 |
4 |
|
T88 |
6 |
| true |
3318 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9963 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T59 |
100 |
| others[1] |
249 |
1 |
|
T79 |
4 |
|
T88 |
7 |
|
T371 |
1 |
| others[2] |
250 |
1 |
|
T16 |
1 |
|
T8 |
1 |
|
T79 |
7 |
| others[3] |
438 |
1 |
|
T18 |
1 |
|
T227 |
1 |
|
T79 |
17 |
| false |
150 |
1 |
|
T29 |
1 |
|
T79 |
9 |
|
T88 |
8 |
| true |
3350 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10561 |
1 |
|
T3 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
771 |
1 |
|
T6 |
1 |
|
T79 |
18 |
|
T88 |
21 |
| others[2] |
774 |
1 |
|
T60 |
1 |
|
T42 |
1 |
|
T79 |
15 |
| others[3] |
1355 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| false |
448 |
1 |
|
T42 |
1 |
|
T79 |
12 |
|
T88 |
8 |
| true |
491 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10506 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
818 |
1 |
|
T6 |
1 |
|
T60 |
1 |
|
T79 |
21 |
| others[2] |
797 |
1 |
|
T79 |
20 |
|
T88 |
18 |
|
T219 |
1 |
| others[3] |
1313 |
1 |
|
T2 |
1 |
|
T42 |
3 |
|
T29 |
1 |
| false |
406 |
1 |
|
T79 |
14 |
|
T88 |
12 |
|
T371 |
1 |
| true |
527 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2546 |
1 |
|
T2 |
1 |
|
T59 |
27 |
|
T60 |
1 |
| others[1] |
2421 |
1 |
|
T6 |
1 |
|
T59 |
12 |
|
T13 |
1 |
| others[2] |
2480 |
1 |
|
T59 |
20 |
|
T46 |
13 |
|
T47 |
6 |
| others[3] |
4088 |
1 |
|
T18 |
1 |
|
T59 |
30 |
|
T13 |
1 |
| false |
1266 |
1 |
|
T59 |
11 |
|
T46 |
3 |
|
T47 |
4 |
| true |
1566 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
281 |
1 |
|
T79 |
6 |
|
T44 |
1 |
|
T88 |
14 |
| others[2] |
286 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| others[3] |
481 |
1 |
|
T61 |
1 |
|
T79 |
13 |
|
T104 |
1 |
| false |
143 |
1 |
|
T4 |
1 |
|
T79 |
6 |
|
T88 |
5 |
| true |
3171 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10215 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
461 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T79 |
10 |
| others[2] |
459 |
1 |
|
T79 |
4 |
|
T88 |
11 |
|
T76 |
1 |
| others[3] |
755 |
1 |
|
T8 |
1 |
|
T79 |
22 |
|
T88 |
14 |
| false |
252 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T35 |
1 |
| true |
2225 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9975 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
265 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T79 |
14 |
| others[2] |
282 |
1 |
|
T8 |
1 |
|
T79 |
13 |
|
T88 |
14 |
| others[3] |
427 |
1 |
|
T4 |
1 |
|
T60 |
1 |
|
T79 |
9 |
| false |
137 |
1 |
|
T79 |
6 |
|
T88 |
6 |
|
T125 |
1 |
| true |
3281 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9992 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
275 |
1 |
|
T60 |
1 |
|
T79 |
12 |
|
T44 |
1 |
| others[2] |
225 |
1 |
|
T79 |
9 |
|
T104 |
1 |
|
T44 |
1 |
| others[3] |
444 |
1 |
|
T6 |
1 |
|
T79 |
21 |
|
T88 |
15 |
| false |
126 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
1 |
| true |
3305 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10548 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T8 |
1 |
| others[1] |
795 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T42 |
1 |
| others[2] |
828 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T60 |
1 |
| others[3] |
1352 |
1 |
|
T12 |
1 |
|
T72 |
1 |
|
T42 |
1 |
| false |
362 |
1 |
|
T79 |
9 |
|
T88 |
9 |
|
T22 |
1 |
| true |
482 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10544 |
1 |
|
T18 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
783 |
1 |
|
T109 |
1 |
|
T42 |
1 |
|
T29 |
1 |
| others[2] |
781 |
1 |
|
T60 |
1 |
|
T72 |
1 |
|
T42 |
1 |
| others[3] |
1339 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T42 |
1 |
| false |
399 |
1 |
|
T16 |
1 |
|
T8 |
1 |
|
T79 |
10 |
| true |
521 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2442 |
1 |
|
T59 |
12 |
|
T13 |
1 |
|
T46 |
4 |
| others[1] |
2419 |
1 |
|
T59 |
18 |
|
T46 |
8 |
|
T47 |
4 |
| others[2] |
2489 |
1 |
|
T2 |
1 |
|
T59 |
28 |
|
T13 |
1 |
| others[3] |
4122 |
1 |
|
T6 |
1 |
|
T59 |
30 |
|
T46 |
14 |
| false |
1321 |
1 |
|
T59 |
12 |
|
T46 |
4 |
|
T47 |
5 |
| true |
1574 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10011 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T59 |
100 |
| others[1] |
278 |
1 |
|
T227 |
1 |
|
T79 |
9 |
|
T88 |
4 |
| others[2] |
261 |
1 |
|
T7 |
1 |
|
T79 |
7 |
|
T44 |
1 |
| others[3] |
454 |
1 |
|
T18 |
1 |
|
T79 |
21 |
|
T44 |
1 |
| false |
138 |
1 |
|
T16 |
1 |
|
T79 |
1 |
|
T88 |
5 |
| true |
3225 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10221 |
1 |
|
T2 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
471 |
1 |
|
T7 |
1 |
|
T60 |
1 |
|
T20 |
1 |
| others[2] |
426 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T79 |
12 |
| others[3] |
746 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T79 |
11 |
| false |
215 |
1 |
|
T17 |
1 |
|
T12 |
1 |
|
T109 |
1 |
| true |
2288 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10001 |
1 |
|
T2 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
240 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T79 |
5 |
| others[2] |
283 |
1 |
|
T6 |
1 |
|
T79 |
6 |
|
T44 |
1 |
| others[3] |
447 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T8 |
1 |
| false |
148 |
1 |
|
T227 |
1 |
|
T79 |
8 |
|
T88 |
6 |
| true |
3248 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9991 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T8 |
1 |
| others[1] |
245 |
1 |
|
T227 |
1 |
|
T79 |
9 |
|
T44 |
1 |
| others[2] |
246 |
1 |
|
T79 |
8 |
|
T88 |
2 |
|
T234 |
1 |
| others[3] |
425 |
1 |
|
T18 |
1 |
|
T72 |
1 |
|
T79 |
20 |
| false |
141 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| true |
3319 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10530 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
796 |
1 |
|
T79 |
16 |
|
T88 |
23 |
|
T89 |
1 |
| others[2] |
830 |
1 |
|
T8 |
1 |
|
T79 |
16 |
|
T88 |
21 |
| others[3] |
1318 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
1 |
| false |
393 |
1 |
|
T6 |
1 |
|
T79 |
8 |
|
T88 |
8 |
| true |
500 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10509 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
798 |
1 |
|
T2 |
1 |
|
T79 |
21 |
|
T88 |
24 |
| others[2] |
796 |
1 |
|
T6 |
1 |
|
T60 |
1 |
|
T42 |
1 |
| others[3] |
1312 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T109 |
1 |
| false |
429 |
1 |
|
T42 |
1 |
|
T79 |
12 |
|
T88 |
12 |
| true |
523 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2497 |
1 |
|
T59 |
18 |
|
T8 |
1 |
|
T46 |
4 |
| others[1] |
2590 |
1 |
|
T18 |
1 |
|
T59 |
17 |
|
T60 |
1 |
| others[2] |
2450 |
1 |
|
T59 |
24 |
|
T46 |
6 |
|
T47 |
4 |
| others[3] |
4086 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| false |
1233 |
1 |
|
T59 |
5 |
|
T13 |
1 |
|
T46 |
2 |
| true |
1511 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10012 |
1 |
|
T17 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
287 |
1 |
|
T79 |
9 |
|
T88 |
14 |
|
T45 |
1 |
| others[2] |
272 |
1 |
|
T7 |
1 |
|
T61 |
1 |
|
T79 |
10 |
| others[3] |
462 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| false |
131 |
1 |
|
T29 |
1 |
|
T79 |
3 |
|
T88 |
3 |
| true |
3203 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10247 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
469 |
1 |
|
T4 |
1 |
|
T60 |
1 |
|
T42 |
1 |
| others[2] |
475 |
1 |
|
T7 |
1 |
|
T35 |
1 |
|
T227 |
1 |
| others[3] |
755 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T42 |
1 |
| false |
256 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T79 |
4 |
| true |
2165 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9982 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
269 |
1 |
|
T60 |
1 |
|
T79 |
9 |
|
T88 |
9 |
| others[2] |
277 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T79 |
9 |
| others[3] |
424 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T79 |
21 |
| false |
127 |
1 |
|
T79 |
3 |
|
T44 |
1 |
|
T88 |
7 |
| true |
3288 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T18 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
256 |
1 |
|
T16 |
1 |
|
T79 |
13 |
|
T88 |
6 |
| others[2] |
257 |
1 |
|
T6 |
1 |
|
T79 |
10 |
|
T88 |
6 |
| others[3] |
399 |
1 |
|
T8 |
1 |
|
T79 |
15 |
|
T44 |
1 |
| false |
144 |
1 |
|
T2 |
1 |
|
T79 |
5 |
|
T88 |
7 |
| true |
3286 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10548 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
787 |
1 |
|
T35 |
1 |
|
T42 |
1 |
|
T79 |
21 |
| others[2] |
846 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| others[3] |
1335 |
1 |
|
T16 |
1 |
|
T60 |
1 |
|
T109 |
1 |
| false |
367 |
1 |
|
T8 |
1 |
|
T79 |
8 |
|
T88 |
7 |
| true |
484 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10578 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
746 |
1 |
|
T3 |
1 |
|
T79 |
24 |
|
T88 |
25 |
| others[2] |
773 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T60 |
1 |
| others[3] |
1342 |
1 |
|
T16 |
1 |
|
T8 |
1 |
|
T42 |
1 |
| false |
407 |
1 |
|
T42 |
2 |
|
T79 |
10 |
|
T88 |
8 |
| true |
521 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2500 |
1 |
|
T2 |
1 |
|
T59 |
18 |
|
T46 |
6 |
| others[1] |
2484 |
1 |
|
T59 |
17 |
|
T13 |
1 |
|
T46 |
6 |
| others[2] |
2452 |
1 |
|
T59 |
20 |
|
T60 |
1 |
|
T8 |
1 |
| others[3] |
4134 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T59 |
35 |
| false |
1235 |
1 |
|
T59 |
10 |
|
T47 |
4 |
|
T79 |
10 |
| true |
1562 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9994 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T60 |
1 |
| others[1] |
282 |
1 |
|
T79 |
8 |
|
T88 |
7 |
|
T45 |
1 |
| others[2] |
261 |
1 |
|
T227 |
1 |
|
T79 |
9 |
|
T88 |
6 |
| others[3] |
452 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T79 |
21 |
| false |
143 |
1 |
|
T79 |
4 |
|
T88 |
6 |
|
T197 |
1 |
| true |
3235 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |