Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10192 |
1 |
|
T17 |
1 |
|
T59 |
100 |
|
T12 |
1 |
| others[1] |
451 |
1 |
|
T3 |
1 |
|
T227 |
1 |
|
T61 |
1 |
| others[2] |
464 |
1 |
|
T29 |
1 |
|
T79 |
3 |
|
T104 |
1 |
| others[3] |
784 |
1 |
|
T7 |
1 |
|
T8 |
1 |
|
T42 |
1 |
| false |
240 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T79 |
8 |
| true |
2236 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
270 |
1 |
|
T16 |
1 |
|
T79 |
10 |
|
T88 |
4 |
| others[2] |
248 |
1 |
|
T2 |
1 |
|
T79 |
10 |
|
T88 |
9 |
| others[3] |
436 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T79 |
12 |
| false |
131 |
1 |
|
T79 |
7 |
|
T88 |
5 |
|
T90 |
1 |
| true |
3257 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10006 |
1 |
|
T18 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
256 |
1 |
|
T227 |
1 |
|
T79 |
7 |
|
T88 |
14 |
| others[2] |
224 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T79 |
6 |
| others[3] |
391 |
1 |
|
T16 |
1 |
|
T72 |
1 |
|
T79 |
19 |
| false |
130 |
1 |
|
T79 |
8 |
|
T88 |
4 |
|
T32 |
1 |
| true |
3360 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10565 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
861 |
1 |
|
T2 |
1 |
|
T79 |
22 |
|
T104 |
1 |
| others[2] |
743 |
1 |
|
T6 |
1 |
|
T60 |
1 |
|
T79 |
20 |
| others[3] |
1285 |
1 |
|
T8 |
1 |
|
T42 |
1 |
|
T79 |
31 |
| false |
432 |
1 |
|
T42 |
2 |
|
T79 |
7 |
|
T88 |
14 |
| true |
481 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10526 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
800 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T29 |
1 |
| others[2] |
768 |
1 |
|
T42 |
1 |
|
T79 |
22 |
|
T88 |
21 |
| others[3] |
1348 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T60 |
1 |
| false |
406 |
1 |
|
T42 |
1 |
|
T79 |
8 |
|
T88 |
11 |
| true |
519 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2498 |
1 |
|
T59 |
16 |
|
T13 |
1 |
|
T46 |
9 |
| others[1] |
2459 |
1 |
|
T59 |
20 |
|
T13 |
1 |
|
T60 |
1 |
| others[2] |
2443 |
1 |
|
T59 |
23 |
|
T46 |
7 |
|
T47 |
6 |
| others[3] |
4135 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T18 |
1 |
| false |
1245 |
1 |
|
T59 |
6 |
|
T46 |
5 |
|
T47 |
3 |
| true |
1587 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9991 |
1 |
|
T7 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
298 |
1 |
|
T17 |
1 |
|
T79 |
10 |
|
T88 |
6 |
| others[2] |
265 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T79 |
7 |
| others[3] |
480 |
1 |
|
T6 |
1 |
|
T72 |
1 |
|
T29 |
1 |
| false |
145 |
1 |
|
T3 |
1 |
|
T227 |
1 |
|
T79 |
3 |
| true |
3188 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10200 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T59 |
100 |
| others[1] |
450 |
1 |
|
T35 |
1 |
|
T79 |
6 |
|
T44 |
1 |
| others[2] |
465 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T79 |
4 |
| others[3] |
780 |
1 |
|
T17 |
1 |
|
T72 |
1 |
|
T109 |
1 |
| false |
263 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T79 |
5 |
| true |
2209 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10056 |
1 |
|
T18 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
284 |
1 |
|
T8 |
1 |
|
T79 |
8 |
|
T88 |
12 |
| others[2] |
263 |
1 |
|
T4 |
1 |
|
T79 |
10 |
|
T88 |
8 |
| others[3] |
441 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T79 |
12 |
| false |
133 |
1 |
|
T2 |
1 |
|
T60 |
1 |
|
T79 |
11 |
| true |
3190 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9972 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
236 |
1 |
|
T8 |
1 |
|
T79 |
8 |
|
T88 |
7 |
| others[2] |
259 |
1 |
|
T79 |
11 |
|
T88 |
11 |
|
T110 |
1 |
| others[3] |
426 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T18 |
1 |
| false |
130 |
1 |
|
T79 |
8 |
|
T88 |
4 |
|
T90 |
3 |
| true |
3344 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10502 |
1 |
|
T6 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
836 |
1 |
|
T12 |
1 |
|
T79 |
28 |
|
T44 |
1 |
| others[2] |
797 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| others[3] |
1290 |
1 |
|
T42 |
2 |
|
T29 |
1 |
|
T79 |
27 |
| false |
438 |
1 |
|
T60 |
1 |
|
T42 |
1 |
|
T79 |
13 |
| true |
504 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10525 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
771 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T60 |
1 |
| others[2] |
808 |
1 |
|
T42 |
1 |
|
T79 |
15 |
|
T44 |
1 |
| others[3] |
1352 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| false |
400 |
1 |
|
T79 |
6 |
|
T88 |
8 |
|
T89 |
1 |
| true |
511 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2430 |
1 |
|
T2 |
1 |
|
T59 |
17 |
|
T13 |
2 |
| others[1] |
2405 |
1 |
|
T59 |
21 |
|
T60 |
1 |
|
T46 |
3 |
| others[2] |
2508 |
1 |
|
T59 |
19 |
|
T8 |
1 |
|
T46 |
9 |
| others[3] |
4131 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T59 |
27 |
| false |
1311 |
1 |
|
T59 |
16 |
|
T46 |
3 |
|
T79 |
5 |
| true |
1582 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10000 |
1 |
|
T17 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
313 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T79 |
10 |
| others[2] |
269 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T79 |
10 |
| others[3] |
461 |
1 |
|
T79 |
18 |
|
T88 |
15 |
|
T73 |
1 |
| false |
154 |
1 |
|
T8 |
1 |
|
T79 |
4 |
|
T44 |
1 |
| true |
3170 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10211 |
1 |
|
T17 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
465 |
1 |
|
T79 |
9 |
|
T44 |
1 |
|
T88 |
9 |
| others[2] |
468 |
1 |
|
T6 |
1 |
|
T79 |
10 |
|
T88 |
13 |
| others[3] |
760 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T227 |
1 |
| false |
244 |
1 |
|
T18 |
1 |
|
T79 |
8 |
|
T88 |
7 |
| true |
2219 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10023 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T8 |
1 |
| others[1] |
234 |
1 |
|
T79 |
8 |
|
T88 |
9 |
|
T32 |
1 |
| others[2] |
255 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T18 |
1 |
| others[3] |
440 |
1 |
|
T16 |
1 |
|
T29 |
1 |
|
T79 |
15 |
| false |
126 |
1 |
|
T4 |
1 |
|
T79 |
5 |
|
T88 |
8 |
| true |
3289 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10011 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
263 |
1 |
|
T79 |
10 |
|
T44 |
1 |
|
T88 |
10 |
| others[2] |
277 |
1 |
|
T79 |
8 |
|
T104 |
1 |
|
T88 |
9 |
| others[3] |
422 |
1 |
|
T8 |
1 |
|
T79 |
18 |
|
T88 |
13 |
| false |
126 |
1 |
|
T18 |
1 |
|
T79 |
2 |
|
T88 |
7 |
| true |
3268 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10537 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
812 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T29 |
1 |
| others[2] |
809 |
1 |
|
T6 |
1 |
|
T79 |
18 |
|
T88 |
20 |
| others[3] |
1297 |
1 |
|
T16 |
1 |
|
T109 |
1 |
|
T42 |
1 |
| false |
424 |
1 |
|
T60 |
1 |
|
T42 |
1 |
|
T79 |
13 |
| true |
488 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10565 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
764 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T79 |
20 |
| others[2] |
837 |
1 |
|
T60 |
1 |
|
T8 |
1 |
|
T79 |
18 |
| others[3] |
1265 |
1 |
|
T3 |
1 |
|
T79 |
35 |
|
T88 |
31 |
| false |
419 |
1 |
|
T2 |
1 |
|
T42 |
2 |
|
T79 |
7 |
| true |
517 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2583 |
1 |
|
T2 |
1 |
|
T59 |
21 |
|
T46 |
3 |
| others[1] |
2491 |
1 |
|
T59 |
19 |
|
T13 |
1 |
|
T46 |
8 |
| others[2] |
2432 |
1 |
|
T59 |
22 |
|
T60 |
1 |
|
T46 |
9 |
| others[3] |
4106 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T59 |
31 |
| false |
1221 |
1 |
|
T59 |
7 |
|
T46 |
4 |
|
T47 |
3 |
| true |
1534 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10042 |
1 |
|
T17 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
289 |
1 |
|
T60 |
1 |
|
T29 |
1 |
|
T79 |
13 |
| others[2] |
261 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T7 |
1 |
| others[3] |
461 |
1 |
|
T3 |
1 |
|
T79 |
18 |
|
T88 |
20 |
| false |
149 |
1 |
|
T8 |
1 |
|
T227 |
1 |
|
T79 |
6 |
| true |
3165 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10196 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
439 |
1 |
|
T79 |
6 |
|
T88 |
7 |
|
T19 |
1 |
| others[2] |
492 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| others[3] |
798 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T18 |
1 |
| false |
245 |
1 |
|
T12 |
1 |
|
T79 |
5 |
|
T44 |
1 |
| true |
2197 |
1 |
|
T16 |
1 |
|
T60 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10006 |
1 |
|
T16 |
1 |
|
T59 |
100 |
|
T13 |
2 |
| others[1] |
259 |
1 |
|
T7 |
1 |
|
T227 |
1 |
|
T79 |
4 |
| others[2] |
263 |
1 |
|
T72 |
1 |
|
T79 |
12 |
|
T88 |
9 |
| others[3] |
444 |
1 |
|
T18 |
1 |
|
T60 |
1 |
|
T29 |
1 |
| false |
145 |
1 |
|
T2 |
1 |
|
T79 |
5 |
|
T88 |
6 |
| true |
3250 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9984 |
1 |
|
T59 |
100 |
|
T13 |
2 |
|
T46 |
34 |
| others[1] |
279 |
1 |
|
T79 |
9 |
|
T88 |
13 |
|
T89 |
1 |
| others[2] |
268 |
1 |
|
T7 |
1 |
|
T79 |
15 |
|
T88 |
14 |
| others[3] |
442 |
1 |
|
T8 |
1 |
|
T29 |
1 |
|
T79 |
9 |
| false |
123 |
1 |
|
T18 |
1 |
|
T79 |
4 |
|
T88 |
2 |
| true |
3271 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10568 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T59 |
100 |
| others[1] |
795 |
1 |
|
T60 |
1 |
|
T8 |
1 |
|
T79 |
20 |
| others[2] |
799 |
1 |
|
T6 |
1 |
|
T42 |
2 |
|
T79 |
20 |
| others[3] |
1292 |
1 |
|
T42 |
1 |
|
T79 |
27 |
|
T88 |
26 |
| false |
414 |
1 |
|
T109 |
1 |
|
T29 |
1 |
|
T79 |
9 |
| true |
499 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |