Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	227166	1		T1	371		T3	36		T4	54
auto[FlashEraseBank]	252616	1		T3	33		T4	15		T16	45

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	265709	1		T1	12		T3	40		T4	34
auto[FlashOpProgram]	193889	1		T1	352		T3	29		T16	87
auto[FlashOpErase]	16184	1		T1	7		T4	35		T16	28
auto[FlashOpInvalid]	4000	1		T59	200		T215	200		T299	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	265709	1		T1	12		T3	40		T4	34
op[FlashOpProgram]	193889	1		T1	352		T3	29		T16	87
op[FlashOpErase]	16184	1		T1	7		T4	35		T16	28
read_erase_read	754	1		T1	1		T4	13		T16	7
read_prog_read	1331	1		T3	29		T16	18		T17	39

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	335610	1		T3	1		T4	58		T16	197
auto[FlashPartInfo]	140325	1		T1	371		T3	68		T4	9
auto[FlashPartInfo1]	902	1		T7	1		T8	4		T44	3
auto[FlashPartInfo2]	2945	1		T4	2		T17	2		T7	8

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	200147	1		T3	1		T4	23		T16	83
auto[FlashPartData]	auto[FlashOpProgram]	127760	1		T16	86		T7	785		T18	1
auto[FlashPartData]	auto[FlashOpErase]	3765	1		T4	35		T16	28		T59	98
auto[FlashPartData]	auto[FlashOpInvalid]	3938	1		T59	196		T215	198		T299	192
auto[FlashPartInfo]	auto[FlashOpRead]	63004	1		T1	12		T3	39		T4	9
auto[FlashPartInfo]	auto[FlashOpProgram]	64872	1		T1	352		T3	29		T16	1
auto[FlashPartInfo]	auto[FlashOpErase]	12397	1		T1	7		T59	2		T46	57
auto[FlashPartInfo]	auto[FlashOpInvalid]	52	1		T59	4		T215	2		T299	8
auto[FlashPartInfo1]	auto[FlashOpRead]	722	1		T7	1		T8	4		T44	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	167	1		T93	1		T119	1		T95	1
auto[FlashPartInfo1]	auto[FlashOpErase]	9	1		T225	1		T91	1		T115	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T96	2		T398	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1836	1		T4	2		T17	2		T7	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	1090	1		T7	3		T60	6		T8	8
auto[FlashPartInfo2]	auto[FlashOpErase]	13	1		T90	1		T226	1		T399	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T400	2		T401	4		-	-