Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31282	1		T16	12		T59	400		T46	108
auto[1]	80	1		T402	1		T211	2		T120	1
auto[2]	163	1		T30	5		T403	2		T404	24
auto[3]	235	1		T20	1		T54	1		T197	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7958	1		T16	3		T59	100		T46	27
evic_idx[1]	7948	1		T16	3		T59	100		T46	27
evic_idx[2]	7930	1		T16	3		T59	100		T46	27
evic_idx[3]	7924	1		T16	3		T59	100		T46	27

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30723	1		T59	400		T46	108		T47	112
evic_op[2]	451	1		T20	1		T42	1		T88	8

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7615	1		T59	100		T46	27		T47	28
evic_idx[0]	evic_op[1]	auto[1]	18	1		T405	17		T406	1		-	-
evic_idx[0]	evic_op[1]	auto[2]	2	1		T407	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	58	1		T208	4		T279	13		T408	6
evic_idx[0]	evic_op[2]	auto[0]	66	1		T88	2		T76	4		T219	4
evic_idx[0]	evic_op[2]	auto[1]	8	1		T402	1		T211	2		T409	1
evic_idx[0]	evic_op[2]	auto[2]	32	1		T404	9		T410	4		T411	2
evic_idx[0]	evic_op[2]	auto[3]	12	1		T111	1		T108	1		T280	1
evic_idx[1]	evic_op[1]	auto[0]	7615	1		T59	100		T46	27		T47	28
evic_idx[1]	evic_op[1]	auto[1]	20	1		T405	17		T406	3		-	-
evic_idx[1]	evic_op[1]	auto[2]	4	1		T407	4		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	52	1		T208	2		T279	16		T408	2
evic_idx[1]	evic_op[2]	auto[0]	66	1		T42	1		T88	2		T76	4
evic_idx[1]	evic_op[2]	auto[1]	4	1		T289	1		T412	1		T212	1
evic_idx[1]	evic_op[2]	auto[2]	30	1		T403	1		T404	6		T410	4
evic_idx[1]	evic_op[2]	auto[3]	10	1		T54	1		T56	1		T413	1
evic_idx[2]	evic_op[1]	auto[0]	7615	1		T59	100		T46	27		T47	28
evic_idx[2]	evic_op[1]	auto[1]	14	1		T405	14		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	3	1		T407	3		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	41	1		T208	2		T279	14		T408	5
evic_idx[2]	evic_op[2]	auto[0]	64	1		T88	2		T76	4		T219	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T120	1		T409	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	32	1		T30	3		T403	1		T404	6
evic_idx[2]	evic_op[2]	auto[3]	13	1		T20	1		T197	1		T280	1
evic_idx[3]	evic_op[1]	auto[0]	7615	1		T59	100		T46	27		T47	28
evic_idx[3]	evic_op[1]	auto[1]	12	1		T405	12		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	3	1		T407	3		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	36	1		T208	5		T279	14		T408	2
evic_idx[3]	evic_op[2]	auto[0]	68	1		T88	2		T76	4		T219	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T409	1		T412	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	29	1		T30	2		T404	3		T410	7
evic_idx[3]	evic_op[2]	auto[3]	13	1		T111	1		T108	1		T199	1