Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	23764	1		T333	10041		T287	2683		T334	1698
rd_lvl[2]	39255	1		T335	5816		T336	6330		T333	5719
rd_lvl[3]	16467	1		T335	556		T337	2795		T336	463
rd_lvl[4]	19410	1		T29	2732		T337	1526		T338	3221
rd_lvl[5]	15607	1		T29	816		T224	1917		T337	1
rd_lvl[6]	17167	1		T19	1222		T224	633		T339	1033
rd_lvl[7]	10142	1		T19	446		T224	1		T340	472
rd_lvl[8]	8396	1		T6	1310		T224	64		T341	781
rd_lvl[9]	7579	1		T6	286		T340	84		T342	1
rd_lvl[10]	6487	1		T27	435		T337	1		T338	1
rd_lvl[11]	7841	1		T224	64		T26	632		T27	357
rd_lvl[12]	7729	1		T26	470		T220	707		T343	38
rd_lvl[13]	4604	1		T27	27		T28	223		T338	82
rd_lvl[14]	8389	1		T26	67		T28	743		T344	601
rd_lvl[15]	5191	1		T344	459		T345	590		T346	421