Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	310357	1		T1	2		T3	1		T4	1
all_pins[1]	310357	1		T1	2		T3	1		T4	1
all_pins[2]	310357	1		T1	2		T3	1		T4	1
all_pins[3]	310357	1		T1	2		T3	1		T4	1
all_pins[4]	310357	1		T1	2		T3	1		T4	1
all_pins[5]	310357	1		T1	2		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1558400	1		T1	12		T3	6		T4	6
values[0x1]	303742	1		T6	2394		T29	4435		T19	2502
transitions[0x0=>0x1]	283429	1		T6	1596		T29	3548		T19	2502
transitions[0x1=>0x0]	283411	1		T6	1596		T29	3548		T19	2502

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	310208	1		T1	2		T3	1		T4	1
all_pins[0]	values[0x1]	149	1		T264	5		T265	1		T266	2
all_pins[0]	transitions[0x0=>0x1]	88	1		T264	5		T266	1		T326	2
all_pins[0]	transitions[0x1=>0x0]	77	1		T265	4		T266	4		T325	3
all_pins[1]	values[0x0]	310219	1		T1	2		T3	1		T4	1
all_pins[1]	values[0x1]	138	1		T265	5		T266	5		T325	3
all_pins[1]	transitions[0x0=>0x1]	109	1		T265	4		T266	5		T325	3
all_pins[1]	transitions[0x1=>0x0]	1536	1		T344	19		T345	409		T346	27
all_pins[2]	values[0x0]	308792	1		T1	2		T3	1		T4	1
all_pins[2]	values[0x1]	1565	1		T344	19		T345	409		T346	27
all_pins[2]	transitions[0x0=>0x1]	46	1		T265	1		T325	1		T327	2
all_pins[2]	transitions[0x1=>0x0]	198192	1		T6	1596		T29	3548		T19	1668
all_pins[3]	values[0x0]	110646	1		T1	2		T3	1		T4	1
all_pins[3]	values[0x1]	199711	1		T6	1596		T29	3548		T19	1668
all_pins[3]	transitions[0x0=>0x1]	181054	1		T6	798		T29	2661		T19	1668
all_pins[3]	transitions[0x1=>0x0]	83461	1		T19	834		T21	1154		T224	1142
all_pins[4]	values[0x0]	208239	1		T1	2		T3	1		T4	1
all_pins[4]	values[0x1]	102118	1		T6	798		T29	887		T19	834
all_pins[4]	transitions[0x0=>0x1]	102100	1		T6	798		T29	887		T19	834
all_pins[4]	transitions[0x1=>0x0]	43	1		T265	2		T327	2		T326	1
all_pins[5]	values[0x0]	310296	1		T1	2		T3	1		T4	1
all_pins[5]	values[0x1]	61	1		T265	2		T266	1		T327	2
all_pins[5]	transitions[0x0=>0x1]	32	1		T265	1		T266	1		T327	1
all_pins[5]	transitions[0x1=>0x0]	102	1		T264	4		T266	2		T327	1