Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T264	4		T265	4		T266	7
all_values[1]	275	1		T264	4		T265	4		T266	7
all_values[2]	275	1		T264	4		T265	4		T266	7
all_values[3]	275	1		T264	4		T265	4		T266	7
all_values[4]	275	1		T264	4		T265	4		T266	7
all_values[5]	275	1		T264	4		T265	4		T266	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	924	1		T264	18		T265	8		T266	27
auto[1]	726	1		T264	6		T265	16		T266	15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	555	1		T264	9		T265	10		T266	14
auto[1]	1095	1		T264	15		T265	14		T266	28

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1004	1		T264	13		T265	15		T266	28
auto[1]	646	1		T264	11		T265	9		T266	14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T265	2		T266	3		T325	4
all_values[0]	auto[0]	auto[1]	auto[1]	77	1		T264	1		T266	1		T326	2
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T264	1		T265	1		T266	2
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T264	2		T265	1		T266	1
all_values[1]	auto[0]	auto[0]	auto[1]	107	1		T264	2		T266	4		T325	2
all_values[1]	auto[0]	auto[1]	auto[1]	74	1		T265	1		T266	3		T325	2
all_values[1]	auto[1]	auto[0]	auto[1]	47	1		T264	2		T327	2		T326	2
all_values[1]	auto[1]	auto[1]	auto[1]	47	1		T265	3		T327	1		T328	2
all_values[2]	auto[0]	auto[0]	auto[0]	96	1		T264	2		T265	1		T266	4
all_values[2]	auto[0]	auto[1]	auto[0]	66	1		T264	1		T265	2		T266	1
all_values[2]	auto[1]	auto[0]	auto[1]	62	1		T264	1		T266	1		T327	3
all_values[2]	auto[1]	auto[1]	auto[1]	51	1		T265	1		T266	1		T325	2
all_values[3]	auto[0]	auto[0]	auto[0]	93	1		T264	1		T266	3		T325	2
all_values[3]	auto[0]	auto[1]	auto[0]	73	1		T265	3		T266	3		T325	1
all_values[3]	auto[1]	auto[0]	auto[1]	72	1		T264	2		T265	1		T266	1
all_values[3]	auto[1]	auto[1]	auto[1]	37	1		T264	1		T327	1		T326	1
all_values[4]	auto[0]	auto[0]	auto[0]	64	1		T264	1		T265	2		T266	2
all_values[4]	auto[0]	auto[0]	auto[1]	23	1		T264	1		T265	1		T326	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1		T264	1		T325	3		T327	2
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T329	1		T330	1		T331	2
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T264	1		T266	3		T325	1
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T265	1		T266	2		T327	1
all_values[5]	auto[0]	auto[0]	auto[0]	64	1		T264	3		T266	1		T327	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T266	2		T327	1		T332	1
all_values[5]	auto[0]	auto[1]	auto[0]	51	1		T265	2		T325	2		T327	1
all_values[5]	auto[0]	auto[1]	auto[1]	28	1		T265	1		T266	1		T327	1
all_values[5]	auto[1]	auto[0]	auto[1]	59	1		T264	1		T266	1		T325	2
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T265	1		T266	2		T327	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal