| T1074 |
/workspace/coverage/default/38.flash_ctrl_disable.394228489 |
|
|
Apr 04 03:29:25 PM PDT 24 |
Apr 04 03:29:45 PM PDT 24 |
18381000 ps |
| T1075 |
/workspace/coverage/default/0.flash_ctrl_re_evict.3871217045 |
|
|
Apr 04 03:16:43 PM PDT 24 |
Apr 04 03:17:13 PM PDT 24 |
313513800 ps |
| T1076 |
/workspace/coverage/default/12.flash_ctrl_mp_regions.2114170086 |
|
|
Apr 04 03:23:24 PM PDT 24 |
Apr 04 03:36:22 PM PDT 24 |
12366657500 ps |
| T1077 |
/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2842736474 |
|
|
Apr 04 03:24:35 PM PDT 24 |
Apr 04 03:26:13 PM PDT 24 |
10015190800 ps |
| T1078 |
/workspace/coverage/default/4.flash_ctrl_smoke_hw.2401307738 |
|
|
Apr 04 03:19:23 PM PDT 24 |
Apr 04 03:19:50 PM PDT 24 |
15228400 ps |
| T1079 |
/workspace/coverage/default/55.flash_ctrl_connect.1459557112 |
|
|
Apr 04 03:30:29 PM PDT 24 |
Apr 04 03:30:42 PM PDT 24 |
49232500 ps |
| T1080 |
/workspace/coverage/default/5.flash_ctrl_smoke.4058519319 |
|
|
Apr 04 03:19:58 PM PDT 24 |
Apr 04 03:22:01 PM PDT 24 |
170073700 ps |
| T1081 |
/workspace/coverage/default/57.flash_ctrl_otp_reset.84989841 |
|
|
Apr 04 03:30:27 PM PDT 24 |
Apr 04 03:32:17 PM PDT 24 |
80875300 ps |
| T1082 |
/workspace/coverage/default/36.flash_ctrl_sec_info_access.1314990607 |
|
|
Apr 04 03:29:00 PM PDT 24 |
Apr 04 03:30:07 PM PDT 24 |
643650000 ps |
| T364 |
/workspace/coverage/default/31.flash_ctrl_disable.23811446 |
|
|
Apr 04 03:28:12 PM PDT 24 |
Apr 04 03:28:34 PM PDT 24 |
15950300 ps |
| T1083 |
/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.85556915 |
|
|
Apr 04 03:21:20 PM PDT 24 |
Apr 04 03:24:44 PM PDT 24 |
9703271100 ps |
| T1084 |
/workspace/coverage/default/36.flash_ctrl_disable.1498514677 |
|
|
Apr 04 03:29:00 PM PDT 24 |
Apr 04 03:29:20 PM PDT 24 |
10228900 ps |
| T1085 |
/workspace/coverage/default/28.flash_ctrl_disable.2190525736 |
|
|
Apr 04 03:27:58 PM PDT 24 |
Apr 04 03:28:19 PM PDT 24 |
21708600 ps |
| T1086 |
/workspace/coverage/default/4.flash_ctrl_sec_info_access.1468946723 |
|
|
Apr 04 03:19:54 PM PDT 24 |
Apr 04 03:20:54 PM PDT 24 |
549065000 ps |
| T1087 |
/workspace/coverage/default/5.flash_ctrl_otp_reset.1316762146 |
|
|
Apr 04 03:20:09 PM PDT 24 |
Apr 04 03:22:21 PM PDT 24 |
136477900 ps |
| T1088 |
/workspace/coverage/default/8.flash_ctrl_ro_serr.3108956989 |
|
|
Apr 04 03:21:47 PM PDT 24 |
Apr 04 03:23:48 PM PDT 24 |
1701698100 ps |
| T1089 |
/workspace/coverage/default/3.flash_ctrl_smoke_hw.1844730488 |
|
|
Apr 04 03:18:25 PM PDT 24 |
Apr 04 03:18:49 PM PDT 24 |
21267300 ps |
| T1090 |
/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.46636326 |
|
|
Apr 04 03:23:07 PM PDT 24 |
Apr 04 03:26:18 PM PDT 24 |
16895660600 ps |
| T1091 |
/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1393759564 |
|
|
Apr 04 03:19:07 PM PDT 24 |
Apr 04 03:19:20 PM PDT 24 |
16156200 ps |
| T1092 |
/workspace/coverage/default/19.flash_ctrl_otp_reset.2015636145 |
|
|
Apr 04 03:26:20 PM PDT 24 |
Apr 04 03:28:30 PM PDT 24 |
39984100 ps |
| T1093 |
/workspace/coverage/default/32.flash_ctrl_sec_info_access.2600542755 |
|
|
Apr 04 03:28:30 PM PDT 24 |
Apr 04 03:29:31 PM PDT 24 |
2257562600 ps |
| T1094 |
/workspace/coverage/default/24.flash_ctrl_sec_info_access.3676690186 |
|
|
Apr 04 03:27:12 PM PDT 24 |
Apr 04 03:28:11 PM PDT 24 |
1712332600 ps |
| T1095 |
/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2390819021 |
|
|
Apr 04 03:17:34 PM PDT 24 |
Apr 04 03:17:48 PM PDT 24 |
61958700 ps |
| T1096 |
/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.399822200 |
|
|
Apr 04 03:28:32 PM PDT 24 |
Apr 04 03:29:04 PM PDT 24 |
31487500 ps |
| T1097 |
/workspace/coverage/default/3.flash_ctrl_fetch_code.1155951597 |
|
|
Apr 04 03:18:28 PM PDT 24 |
Apr 04 03:18:52 PM PDT 24 |
488161900 ps |
| T1098 |
/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1913864364 |
|
|
Apr 04 03:22:53 PM PDT 24 |
Apr 04 03:23:07 PM PDT 24 |
37622300 ps |
| T1099 |
/workspace/coverage/default/4.flash_ctrl_wo.2878083262 |
|
|
Apr 04 03:19:26 PM PDT 24 |
Apr 04 03:22:35 PM PDT 24 |
2124937200 ps |
| T1100 |
/workspace/coverage/default/2.flash_ctrl_full_mem_access.4210236298 |
|
|
Apr 04 03:17:41 PM PDT 24 |
Apr 04 04:27:16 PM PDT 24 |
113477528100 ps |
| T1101 |
/workspace/coverage/default/10.flash_ctrl_sec_info_access.1052324226 |
|
|
Apr 04 03:22:53 PM PDT 24 |
Apr 04 03:23:56 PM PDT 24 |
1851713300 ps |
| T1102 |
/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1214845755 |
|
|
Apr 04 03:26:47 PM PDT 24 |
Apr 04 03:30:32 PM PDT 24 |
17364615700 ps |
| T1103 |
/workspace/coverage/default/78.flash_ctrl_otp_reset.864553552 |
|
|
Apr 04 03:30:51 PM PDT 24 |
Apr 04 03:32:38 PM PDT 24 |
37168100 ps |
| T1104 |
/workspace/coverage/default/39.flash_ctrl_connect.5637103 |
|
|
Apr 04 03:29:26 PM PDT 24 |
Apr 04 03:29:41 PM PDT 24 |
26060900 ps |
| T1105 |
/workspace/coverage/default/2.flash_ctrl_host_dir_rd.2683406782 |
|
|
Apr 04 03:17:43 PM PDT 24 |
Apr 04 03:19:35 PM PDT 24 |
62337200 ps |
| T1106 |
/workspace/coverage/default/14.flash_ctrl_prog_reset.3734820869 |
|
|
Apr 04 03:24:20 PM PDT 24 |
Apr 04 03:24:34 PM PDT 24 |
57578400 ps |
| T1107 |
/workspace/coverage/default/19.flash_ctrl_mp_regions.724057366 |
|
|
Apr 04 03:26:18 PM PDT 24 |
Apr 04 03:31:19 PM PDT 24 |
35990591000 ps |
| T1108 |
/workspace/coverage/default/3.flash_ctrl_oversize_error.191768055 |
|
|
Apr 04 03:18:53 PM PDT 24 |
Apr 04 03:21:50 PM PDT 24 |
4421707100 ps |
| T1109 |
/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.193971120 |
|
|
Apr 04 03:19:57 PM PDT 24 |
Apr 04 03:21:37 PM PDT 24 |
10012455700 ps |
| T1110 |
/workspace/coverage/default/4.flash_ctrl_full_mem_access.487953538 |
|
|
Apr 04 03:19:23 PM PDT 24 |
Apr 04 04:18:59 PM PDT 24 |
50870675300 ps |
| T1111 |
/workspace/coverage/default/17.flash_ctrl_rand_ops.922492262 |
|
|
Apr 04 03:25:07 PM PDT 24 |
Apr 04 03:38:35 PM PDT 24 |
214182400 ps |
| T1112 |
/workspace/coverage/default/40.flash_ctrl_otp_reset.839106123 |
|
|
Apr 04 03:29:43 PM PDT 24 |
Apr 04 03:31:56 PM PDT 24 |
41631200 ps |
| T221 |
/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3106321740 |
|
|
Apr 04 03:16:57 PM PDT 24 |
Apr 04 03:18:09 PM PDT 24 |
685703400 ps |
| T1113 |
/workspace/coverage/default/26.flash_ctrl_smoke.977596498 |
|
|
Apr 04 03:27:27 PM PDT 24 |
Apr 04 03:28:17 PM PDT 24 |
30340700 ps |
| T1114 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1552084696 |
|
|
Apr 04 03:25:21 PM PDT 24 |
Apr 04 03:40:07 PM PDT 24 |
80152103900 ps |
| T1115 |
/workspace/coverage/default/1.flash_ctrl_alert_test.2587264649 |
|
|
Apr 04 03:17:27 PM PDT 24 |
Apr 04 03:17:41 PM PDT 24 |
30262500 ps |
| T1116 |
/workspace/coverage/default/14.flash_ctrl_disable.1498343022 |
|
|
Apr 04 03:24:23 PM PDT 24 |
Apr 04 03:24:45 PM PDT 24 |
13082900 ps |
| T1117 |
/workspace/coverage/default/65.flash_ctrl_connect.2230640409 |
|
|
Apr 04 03:30:41 PM PDT 24 |
Apr 04 03:30:54 PM PDT 24 |
19331400 ps |
| T1118 |
/workspace/coverage/default/74.flash_ctrl_connect.3109752041 |
|
|
Apr 04 03:30:46 PM PDT 24 |
Apr 04 03:31:01 PM PDT 24 |
81913300 ps |
| T1119 |
/workspace/coverage/default/18.flash_ctrl_mp_regions.2001599381 |
|
|
Apr 04 03:26:00 PM PDT 24 |
Apr 04 03:29:12 PM PDT 24 |
19553652500 ps |
| T251 |
/workspace/coverage/default/0.flash_ctrl_integrity.368303573 |
|
|
Apr 04 03:16:43 PM PDT 24 |
Apr 04 03:26:17 PM PDT 24 |
3573812900 ps |
| T1120 |
/workspace/coverage/default/46.flash_ctrl_alert_test.2492497203 |
|
|
Apr 04 03:30:22 PM PDT 24 |
Apr 04 03:30:36 PM PDT 24 |
112911300 ps |
| T1121 |
/workspace/coverage/default/7.flash_ctrl_ro_serr.1194938259 |
|
|
Apr 04 03:21:22 PM PDT 24 |
Apr 04 03:23:49 PM PDT 24 |
2570123500 ps |
| T1122 |
/workspace/coverage/default/2.flash_ctrl_otp_reset.3486022910 |
|
|
Apr 04 03:17:43 PM PDT 24 |
Apr 04 03:19:33 PM PDT 24 |
148135900 ps |
| T1123 |
/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3225758103 |
|
|
Apr 04 03:24:05 PM PDT 24 |
Apr 04 03:27:53 PM PDT 24 |
16521139100 ps |
| T1124 |
/workspace/coverage/default/57.flash_ctrl_connect.2595382337 |
|
|
Apr 04 03:30:30 PM PDT 24 |
Apr 04 03:30:46 PM PDT 24 |
22519300 ps |
| T1125 |
/workspace/coverage/default/52.flash_ctrl_otp_reset.1956814733 |
|
|
Apr 04 03:30:23 PM PDT 24 |
Apr 04 03:32:33 PM PDT 24 |
82437200 ps |
| T1126 |
/workspace/coverage/default/15.flash_ctrl_ro.3840730665 |
|
|
Apr 04 03:24:37 PM PDT 24 |
Apr 04 03:26:37 PM PDT 24 |
502471200 ps |
| T1127 |
/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3637968287 |
|
|
Apr 04 03:28:14 PM PDT 24 |
Apr 04 03:28:45 PM PDT 24 |
81107500 ps |
| T1128 |
/workspace/coverage/default/6.flash_ctrl_rw_evict.3923822107 |
|
|
Apr 04 03:21:09 PM PDT 24 |
Apr 04 03:21:39 PM PDT 24 |
160813700 ps |
| T202 |
/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3482301581 |
|
|
Apr 04 03:17:41 PM PDT 24 |
Apr 04 03:58:57 PM PDT 24 |
243773446900 ps |
| T1129 |
/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1323132116 |
|
|
Apr 04 03:18:54 PM PDT 24 |
Apr 04 03:19:27 PM PDT 24 |
28576100 ps |
| T1130 |
/workspace/coverage/default/17.flash_ctrl_ro.3461791741 |
|
|
Apr 04 03:25:20 PM PDT 24 |
Apr 04 03:27:13 PM PDT 24 |
1135143500 ps |
| T1131 |
/workspace/coverage/default/9.flash_ctrl_smoke.3901511849 |
|
|
Apr 04 03:22:15 PM PDT 24 |
Apr 04 03:23:32 PM PDT 24 |
23800100 ps |
| T1132 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3766420998 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:38:23 PM PDT 24 |
39823800 ps |
| T1133 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4011983385 |
|
|
Apr 04 02:38:15 PM PDT 24 |
Apr 04 02:38:28 PM PDT 24 |
110175700 ps |
| T264 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3649521527 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:31 PM PDT 24 |
30753000 ps |
| T179 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1402965245 |
|
|
Apr 04 02:38:05 PM PDT 24 |
Apr 04 02:38:22 PM PDT 24 |
135864800 ps |
| T265 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.235547538 |
|
|
Apr 04 02:38:30 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
17318700 ps |
| T1134 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3016765153 |
|
|
Apr 04 02:38:05 PM PDT 24 |
Apr 04 02:38:19 PM PDT 24 |
18552100 ps |
| T266 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.327800297 |
|
|
Apr 04 02:38:38 PM PDT 24 |
Apr 04 02:38:52 PM PDT 24 |
25946900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1846798924 |
|
|
Apr 04 02:38:06 PM PDT 24 |
Apr 04 02:38:22 PM PDT 24 |
42018600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.190586204 |
|
|
Apr 04 02:38:32 PM PDT 24 |
Apr 04 02:38:45 PM PDT 24 |
58813300 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2046516677 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:39 PM PDT 24 |
39432400 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1846290641 |
|
|
Apr 04 02:38:04 PM PDT 24 |
Apr 04 02:53:00 PM PDT 24 |
2854213300 ps |
| T192 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3065513476 |
|
|
Apr 04 02:38:08 PM PDT 24 |
Apr 04 02:38:28 PM PDT 24 |
50740900 ps |
| T325 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.669957099 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:32 PM PDT 24 |
74238100 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2095633802 |
|
|
Apr 04 02:38:03 PM PDT 24 |
Apr 04 02:38:48 PM PDT 24 |
99368800 ps |
| T180 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1773574264 |
|
|
Apr 04 02:38:22 PM PDT 24 |
Apr 04 02:38:39 PM PDT 24 |
583310100 ps |
| T327 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2229727347 |
|
|
Apr 04 02:38:12 PM PDT 24 |
Apr 04 02:38:26 PM PDT 24 |
33399400 ps |
| T252 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.894885655 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
101979700 ps |
| T326 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1304768835 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:38:21 PM PDT 24 |
32793400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3490616144 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
19204200 ps |
| T228 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1040342339 |
|
|
Apr 04 02:38:08 PM PDT 24 |
Apr 04 02:38:27 PM PDT 24 |
603755000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1750312817 |
|
|
Apr 04 02:38:16 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
31683800 ps |
| T238 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1227413367 |
|
|
Apr 04 02:38:08 PM PDT 24 |
Apr 04 02:38:21 PM PDT 24 |
19116900 ps |
| T253 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1981351636 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:39 PM PDT 24 |
153548600 ps |
| T193 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1466251745 |
|
|
Apr 04 02:38:12 PM PDT 24 |
Apr 04 02:45:46 PM PDT 24 |
918648500 ps |
| T229 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4116651743 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
124617800 ps |
| T328 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.23360886 |
|
|
Apr 04 02:38:31 PM PDT 24 |
Apr 04 02:38:44 PM PDT 24 |
15297300 ps |
| T358 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.333030223 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
214419700 ps |
| T1139 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.983645882 |
|
|
Apr 04 02:38:04 PM PDT 24 |
Apr 04 02:38:20 PM PDT 24 |
15169400 ps |
| T1140 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.978219717 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:32 PM PDT 24 |
140337300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1261352255 |
|
|
Apr 04 02:37:59 PM PDT 24 |
Apr 04 02:38:12 PM PDT 24 |
28076200 ps |
| T1142 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1398283530 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
14807200 ps |
| T1143 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1628195231 |
|
|
Apr 04 02:38:27 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
51724700 ps |
| T1144 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1979565663 |
|
|
Apr 04 02:38:34 PM PDT 24 |
Apr 04 02:38:48 PM PDT 24 |
17445800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3362854731 |
|
|
Apr 04 02:38:06 PM PDT 24 |
Apr 04 02:38:20 PM PDT 24 |
51495200 ps |
| T415 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2750628168 |
|
|
Apr 04 02:38:32 PM PDT 24 |
Apr 04 02:38:48 PM PDT 24 |
34423300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.258314909 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:30 PM PDT 24 |
31672200 ps |
| T230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3839849666 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:31 PM PDT 24 |
64590000 ps |
| T332 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1714201542 |
|
|
Apr 04 02:38:44 PM PDT 24 |
Apr 04 02:38:58 PM PDT 24 |
53102600 ps |
| T329 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4205131406 |
|
|
Apr 04 02:38:29 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
60257200 ps |
| T1147 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1715789395 |
|
|
Apr 04 02:38:09 PM PDT 24 |
Apr 04 02:38:25 PM PDT 24 |
35632800 ps |
| T1148 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4280211977 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:56 PM PDT 24 |
689461500 ps |
| T231 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.685126079 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:37 PM PDT 24 |
47497700 ps |
| T301 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3264554635 |
|
|
Apr 04 02:38:00 PM PDT 24 |
Apr 04 02:38:17 PM PDT 24 |
253669200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1329296020 |
|
|
Apr 04 02:38:33 PM PDT 24 |
Apr 04 02:38:51 PM PDT 24 |
170152800 ps |
| T232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2999527701 |
|
|
Apr 04 02:37:58 PM PDT 24 |
Apr 04 02:45:36 PM PDT 24 |
348696400 ps |
| T233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1668941319 |
|
|
Apr 04 02:38:01 PM PDT 24 |
Apr 04 02:38:19 PM PDT 24 |
43459600 ps |
| T259 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.4236135400 |
|
|
Apr 04 02:38:10 PM PDT 24 |
Apr 04 02:38:30 PM PDT 24 |
312262900 ps |
| T276 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3156475457 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:52:49 PM PDT 24 |
831807200 ps |
| T1150 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3241066050 |
|
|
Apr 04 02:38:43 PM PDT 24 |
Apr 04 02:38:57 PM PDT 24 |
68682200 ps |
| T330 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1409842506 |
|
|
Apr 04 02:38:30 PM PDT 24 |
Apr 04 02:38:44 PM PDT 24 |
33772000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3636804552 |
|
|
Apr 04 02:38:00 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
219436200 ps |
| T1152 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3392253522 |
|
|
Apr 04 02:38:29 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
26238600 ps |
| T302 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4026941753 |
|
|
Apr 04 02:38:13 PM PDT 24 |
Apr 04 02:38:28 PM PDT 24 |
42573100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3583651590 |
|
|
Apr 04 02:38:27 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
30716000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2425149449 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
14342400 ps |
| T1155 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3591021483 |
|
|
Apr 04 02:38:27 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
81259600 ps |
| T270 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1118429301 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:50:46 PM PDT 24 |
709177500 ps |
| T1156 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1573199973 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:35 PM PDT 24 |
13353900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2988195557 |
|
|
Apr 04 02:38:27 PM PDT 24 |
Apr 04 02:38:45 PM PDT 24 |
32948600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3587695073 |
|
|
Apr 04 02:38:03 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
18472800 ps |
| T273 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1734021080 |
|
|
Apr 04 02:38:04 PM PDT 24 |
Apr 04 02:38:23 PM PDT 24 |
44004200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.530591037 |
|
|
Apr 04 02:38:33 PM PDT 24 |
Apr 04 02:38:50 PM PDT 24 |
38369800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3627795983 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
43454000 ps |
| T1161 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1053772639 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:35 PM PDT 24 |
33177100 ps |
| T260 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.15738150 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:38:24 PM PDT 24 |
445446200 ps |
| T1162 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3568078537 |
|
|
Apr 04 02:38:13 PM PDT 24 |
Apr 04 02:38:26 PM PDT 24 |
33948500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3129816792 |
|
|
Apr 04 02:38:03 PM PDT 24 |
Apr 04 02:38:17 PM PDT 24 |
21659100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4117049915 |
|
|
Apr 04 02:38:35 PM PDT 24 |
Apr 04 02:38:52 PM PDT 24 |
13078900 ps |
| T268 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2488952385 |
|
|
Apr 04 02:38:00 PM PDT 24 |
Apr 04 02:38:16 PM PDT 24 |
102148000 ps |
| T351 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2172031757 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:45:52 PM PDT 24 |
718548100 ps |
| T1165 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.238780897 |
|
|
Apr 04 02:38:16 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
17246400 ps |
| T239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3555907577 |
|
|
Apr 04 02:38:00 PM PDT 24 |
Apr 04 02:38:14 PM PDT 24 |
44912200 ps |
| T303 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.636631999 |
|
|
Apr 04 02:38:00 PM PDT 24 |
Apr 04 02:38:20 PM PDT 24 |
111652000 ps |
| T267 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.605944249 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:37 PM PDT 24 |
77328900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2480968602 |
|
|
Apr 04 02:37:58 PM PDT 24 |
Apr 04 02:38:37 PM PDT 24 |
334478400 ps |
| T331 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2484128751 |
|
|
Apr 04 02:38:28 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
59630200 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1011425175 |
|
|
Apr 04 02:38:06 PM PDT 24 |
Apr 04 02:39:01 PM PDT 24 |
662665400 ps |
| T1168 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2294658553 |
|
|
Apr 04 02:38:33 PM PDT 24 |
Apr 04 02:38:47 PM PDT 24 |
153848300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2874474426 |
|
|
Apr 04 02:38:02 PM PDT 24 |
Apr 04 02:38:15 PM PDT 24 |
13405800 ps |
| T1170 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1174110358 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:27 PM PDT 24 |
95266900 ps |
| T1171 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3877453130 |
|
|
Apr 04 02:38:28 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
41311300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1812433115 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
50989300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3044546221 |
|
|
Apr 04 02:38:01 PM PDT 24 |
Apr 04 02:38:16 PM PDT 24 |
35406200 ps |
| T304 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2498834010 |
|
|
Apr 04 02:38:13 PM PDT 24 |
Apr 04 02:38:49 PM PDT 24 |
839882300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3547885966 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
36250500 ps |
| T349 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.824015144 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:53:12 PM PDT 24 |
729435900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3715847780 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:37 PM PDT 24 |
84276500 ps |
| T305 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.711953795 |
|
|
Apr 04 02:38:16 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
108481500 ps |
| T275 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.269112577 |
|
|
Apr 04 02:38:15 PM PDT 24 |
Apr 04 02:53:06 PM PDT 24 |
3487768500 ps |
| T1176 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1838161194 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
14393500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3499008754 |
|
|
Apr 04 02:38:21 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
28593800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.72043686 |
|
|
Apr 04 02:38:02 PM PDT 24 |
Apr 04 02:38:15 PM PDT 24 |
14074200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1298722761 |
|
|
Apr 04 02:38:13 PM PDT 24 |
Apr 04 02:38:27 PM PDT 24 |
25297100 ps |
| T1180 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3176020342 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:32 PM PDT 24 |
52814900 ps |
| T1181 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3335199259 |
|
|
Apr 04 02:38:42 PM PDT 24 |
Apr 04 02:38:56 PM PDT 24 |
27519000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3143100438 |
|
|
Apr 04 02:38:05 PM PDT 24 |
Apr 04 02:38:58 PM PDT 24 |
438845000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1942366521 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:35 PM PDT 24 |
172242800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2494154130 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
1052848700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1534380838 |
|
|
Apr 04 02:38:09 PM PDT 24 |
Apr 04 02:38:27 PM PDT 24 |
37536200 ps |
| T352 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1582855012 |
|
|
Apr 04 02:38:36 PM PDT 24 |
Apr 04 02:44:57 PM PDT 24 |
668213800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2267525841 |
|
|
Apr 04 02:38:38 PM PDT 24 |
Apr 04 02:38:51 PM PDT 24 |
15275600 ps |
| T1187 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2177685481 |
|
|
Apr 04 02:38:00 PM PDT 24 |
Apr 04 02:38:14 PM PDT 24 |
54185000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.520256299 |
|
|
Apr 04 02:38:09 PM PDT 24 |
Apr 04 02:38:24 PM PDT 24 |
43767000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1413984060 |
|
|
Apr 04 02:38:21 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
59800400 ps |
| T240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.400605345 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:27 PM PDT 24 |
56120600 ps |
| T271 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3410261737 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
30105800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2895831595 |
|
|
Apr 04 02:38:32 PM PDT 24 |
Apr 04 02:38:50 PM PDT 24 |
131501500 ps |
| T356 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.690342903 |
|
|
Apr 04 02:38:12 PM PDT 24 |
Apr 04 02:50:46 PM PDT 24 |
662922400 ps |
| T274 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3480443467 |
|
|
Apr 04 02:38:21 PM PDT 24 |
Apr 04 02:45:57 PM PDT 24 |
1758979600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.199010875 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:30 PM PDT 24 |
38718400 ps |
| T1192 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1837340372 |
|
|
Apr 04 02:38:32 PM PDT 24 |
Apr 04 02:38:46 PM PDT 24 |
20865400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1743065298 |
|
|
Apr 04 02:38:09 PM PDT 24 |
Apr 04 02:38:23 PM PDT 24 |
27125900 ps |
| T1194 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2503493176 |
|
|
Apr 04 02:37:58 PM PDT 24 |
Apr 04 02:38:12 PM PDT 24 |
23883200 ps |
| T306 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2956687193 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
276168800 ps |
| T261 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2834042781 |
|
|
Apr 04 02:38:09 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
1100955600 ps |
| T308 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1157949761 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:35 PM PDT 24 |
128946800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.454206854 |
|
|
Apr 04 02:38:24 PM PDT 24 |
Apr 04 02:38:40 PM PDT 24 |
13578600 ps |
| T1196 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1986126006 |
|
|
Apr 04 02:38:28 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
233591000 ps |
| T1197 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4176506022 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
44358700 ps |
| T1198 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.106308740 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
37404700 ps |
| T307 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2848901048 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:35 PM PDT 24 |
95031700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.4037204465 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
21565900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.865002909 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:30 PM PDT 24 |
11440400 ps |
| T1201 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1906758071 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
65556900 ps |
| T357 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2571572858 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:53:06 PM PDT 24 |
347019900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1044239857 |
|
|
Apr 04 02:38:29 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
18587100 ps |
| T1203 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.281313396 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:32 PM PDT 24 |
32883000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2861442842 |
|
|
Apr 04 02:38:26 PM PDT 24 |
Apr 04 02:38:44 PM PDT 24 |
48852800 ps |
| T262 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.157797149 |
|
|
Apr 04 02:38:15 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
101890600 ps |
| T241 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2239293339 |
|
|
Apr 04 02:38:08 PM PDT 24 |
Apr 04 02:38:22 PM PDT 24 |
114566800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.754296504 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:36 PM PDT 24 |
87168400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3403284566 |
|
|
Apr 04 02:38:32 PM PDT 24 |
Apr 04 02:38:46 PM PDT 24 |
91737500 ps |
| T309 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3204550174 |
|
|
Apr 04 02:38:11 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
57886600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3180574607 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
42871900 ps |
| T1208 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4009687095 |
|
|
Apr 04 02:38:08 PM PDT 24 |
Apr 04 02:38:26 PM PDT 24 |
530369500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1020558800 |
|
|
Apr 04 02:38:28 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
18841400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2424970450 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:27 PM PDT 24 |
11237200 ps |
| T272 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.369969456 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
277246700 ps |
| T355 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2549526483 |
|
|
Apr 04 02:38:03 PM PDT 24 |
Apr 04 02:44:26 PM PDT 24 |
465973400 ps |
| T1211 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.623057392 |
|
|
Apr 04 02:38:12 PM PDT 24 |
Apr 04 02:38:32 PM PDT 24 |
139237300 ps |
| T1212 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1557517051 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:38:22 PM PDT 24 |
288374800 ps |
| T310 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1063548487 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:39 PM PDT 24 |
218669700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.849463857 |
|
|
Apr 04 02:38:10 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
229045500 ps |
| T263 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.809977552 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:42 PM PDT 24 |
49730600 ps |
| T350 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4087203809 |
|
|
Apr 04 02:38:20 PM PDT 24 |
Apr 04 02:44:47 PM PDT 24 |
379293700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2349680975 |
|
|
Apr 04 02:38:28 PM PDT 24 |
Apr 04 02:38:42 PM PDT 24 |
44714600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2607241589 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
30542300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2809812893 |
|
|
Apr 04 02:38:18 PM PDT 24 |
Apr 04 02:45:55 PM PDT 24 |
1419494800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2902134804 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:49 PM PDT 24 |
79778500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1162656994 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:30 PM PDT 24 |
16515500 ps |
| T277 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3836613807 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:53:14 PM PDT 24 |
678142200 ps |
| T311 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2200752514 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:38:24 PM PDT 24 |
382624400 ps |
| T1219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2049545214 |
|
|
Apr 04 02:37:59 PM PDT 24 |
Apr 04 02:38:15 PM PDT 24 |
516484600 ps |
| T1220 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1616203687 |
|
|
Apr 04 02:38:03 PM PDT 24 |
Apr 04 02:38:18 PM PDT 24 |
264992800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4281838779 |
|
|
Apr 04 02:38:10 PM PDT 24 |
Apr 04 02:38:37 PM PDT 24 |
33064100 ps |
| T1222 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2434570754 |
|
|
Apr 04 02:38:01 PM PDT 24 |
Apr 04 02:38:17 PM PDT 24 |
34916700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.925080462 |
|
|
Apr 04 02:38:05 PM PDT 24 |
Apr 04 02:38:21 PM PDT 24 |
194288100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.964354850 |
|
|
Apr 04 02:38:13 PM PDT 24 |
Apr 04 02:38:29 PM PDT 24 |
14378700 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.638454831 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
106424500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1434161083 |
|
|
Apr 04 02:38:11 PM PDT 24 |
Apr 04 02:38:28 PM PDT 24 |
76679400 ps |
| T1227 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.868113630 |
|
|
Apr 04 02:38:36 PM PDT 24 |
Apr 04 02:38:50 PM PDT 24 |
18449300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2773393871 |
|
|
Apr 04 02:38:44 PM PDT 24 |
Apr 04 02:39:18 PM PDT 24 |
65769700 ps |
| T353 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2546730438 |
|
|
Apr 04 02:38:10 PM PDT 24 |
Apr 04 02:52:44 PM PDT 24 |
928695600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3140917047 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:57 PM PDT 24 |
641504200 ps |
| T1230 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1100471685 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:38:33 PM PDT 24 |
107458600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3297429580 |
|
|
Apr 04 02:38:14 PM PDT 24 |
Apr 04 02:45:50 PM PDT 24 |
2925201800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.151580936 |
|
|
Apr 04 02:38:19 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
11769900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2701120733 |
|
|
Apr 04 02:38:07 PM PDT 24 |
Apr 04 02:38:24 PM PDT 24 |
20856400 ps |
| T1234 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1029158959 |
|
|
Apr 04 02:38:29 PM PDT 24 |
Apr 04 02:38:43 PM PDT 24 |
49022900 ps |
| T1235 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2810495943 |
|
|
Apr 04 02:38:11 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
2117775700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3891521839 |
|
|
Apr 04 02:37:58 PM PDT 24 |
Apr 04 02:39:19 PM PDT 24 |
4482892500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.624800526 |
|
|
Apr 04 02:38:33 PM PDT 24 |
Apr 04 02:38:46 PM PDT 24 |
15592900 ps |
| T1238 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2061172121 |
|
|
Apr 04 02:38:05 PM PDT 24 |
Apr 04 02:39:17 PM PDT 24 |
1790901700 ps |
| T1239 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2420314515 |
|
|
Apr 04 02:38:36 PM PDT 24 |
Apr 04 02:38:51 PM PDT 24 |
105346400 ps |
| T1240 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2632673611 |
|
|
Apr 04 02:38:27 PM PDT 24 |
Apr 04 02:38:41 PM PDT 24 |
92314000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2790013379 |
|
|
Apr 04 02:38:46 PM PDT 24 |
Apr 04 02:38:59 PM PDT 24 |
18177100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1293747974 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:31 PM PDT 24 |
22148300 ps |
| T1243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.4126790538 |
|
|
Apr 04 02:38:15 PM PDT 24 |
Apr 04 02:38:35 PM PDT 24 |
394416300 ps |
| T1244 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1884085515 |
|
|
Apr 04 02:38:32 PM PDT 24 |
Apr 04 02:38:46 PM PDT 24 |
30512900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1856184147 |
|
|
Apr 04 02:38:09 PM PDT 24 |
Apr 04 02:38:22 PM PDT 24 |
51725800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.625280810 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:31 PM PDT 24 |
53587300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1222996910 |
|
|
Apr 04 02:37:58 PM PDT 24 |
Apr 04 02:38:12 PM PDT 24 |
22866700 ps |
| T1248 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1950290687 |
|
|
Apr 04 02:38:34 PM PDT 24 |
Apr 04 02:38:48 PM PDT 24 |
16508700 ps |
| T269 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2574673819 |
|
|
Apr 04 02:38:42 PM PDT 24 |
Apr 04 02:38:58 PM PDT 24 |
58016400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3212489464 |
|
|
Apr 04 02:38:08 PM PDT 24 |
Apr 04 02:38:39 PM PDT 24 |
320021300 ps |
| T242 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3242566961 |
|
|
Apr 04 02:38:03 PM PDT 24 |
Apr 04 02:38:16 PM PDT 24 |
53009700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4234209642 |
|
|
Apr 04 02:38:17 PM PDT 24 |
Apr 04 02:38:34 PM PDT 24 |
40063800 ps |
| T1251 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.544953225 |
|
|
Apr 04 02:37:56 PM PDT 24 |
Apr 04 02:38:53 PM PDT 24 |
1267800000 ps |