Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	309897	1		T1	2		T2	2		T3	1
all_values[1]	309897	1		T1	2		T2	2		T3	1
all_values[2]	309897	1		T1	2		T2	2		T3	1
all_values[3]	309897	1		T1	2		T2	2		T3	1
all_values[4]	309897	1		T1	2		T2	2		T3	1
all_values[5]	309897	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	626295	1		T1	12		T2	12		T3	6
auto[1]	1233087	1		T22	4536		T25	4744		T31	25260

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	906344	1		T1	7		T2	7		T3	4
auto[1]	953038	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	309722	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	175	1		T250	4		T251	7		T325	2
all_values[1]	auto[0]	auto[1]	309738	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	159	1		T250	1		T251	4		T325	3
all_values[2]	auto[0]	auto[0]	1641	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	66	1		T250	2		T251	3		T325	1
all_values[2]	auto[1]	auto[0]	308136	1		T22	1134		T25	1186		T31	6315
all_values[2]	auto[1]	auto[1]	54	1		T325	2		T326	1		T327	1
all_values[3]	auto[0]	auto[0]	1645	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	57	1		T250	1		T251	2		T326	2
all_values[3]	auto[1]	auto[0]	75833	1		T22	1134		T25	1186		T31	70
all_values[3]	auto[1]	auto[1]	232362	1		T31	6245		T32	1096		T28	778
all_values[4]	auto[0]	auto[0]	1176	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	543	1		T1	1		T2	1		T4	1
all_values[4]	auto[1]	auto[0]	208236	1		T22	1		T25	1		T31	5290
all_values[4]	auto[1]	auto[1]	99942	1		T22	1133		T25	1185		T31	1025
all_values[5]	auto[0]	auto[0]	1547	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	160	1		T33	1		T34	1		T35	1
all_values[5]	auto[1]	auto[0]	308130	1		T22	1134		T25	1186		T31	6315
all_values[5]	auto[1]	auto[1]	60	1		T250	2		T251	2		T326	2