Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T31 |
1 |
| others[1] |
210 |
1 |
|
T2 |
1 |
|
T21 |
2 |
|
T393 |
1 |
| others[2] |
198 |
1 |
|
T246 |
2 |
|
T103 |
7 |
|
T265 |
1 |
| others[3] |
365 |
1 |
|
T23 |
1 |
|
T159 |
1 |
|
T35 |
1 |
| false |
137 |
1 |
|
T64 |
1 |
|
T237 |
1 |
|
T95 |
1 |
| true |
12940 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
192 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T57 |
1 |
| others[1] |
225 |
1 |
|
T43 |
1 |
|
T35 |
1 |
|
T56 |
1 |
| others[2] |
203 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T64 |
1 |
| others[3] |
393 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T393 |
1 |
| false |
116 |
1 |
|
T392 |
1 |
|
T103 |
4 |
|
T240 |
1 |
| true |
12965 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8477 |
1 |
|
T1 |
7 |
|
T4 |
21 |
|
T59 |
1 |
| others[1] |
1200 |
1 |
|
T1 |
12 |
|
T4 |
13 |
|
T21 |
2 |
| others[2] |
1230 |
1 |
|
T1 |
9 |
|
T4 |
16 |
|
T53 |
11 |
| others[3] |
2098 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
37 |
| false |
659 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
13 |
| true |
430 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8510 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
17 |
| others[1] |
1220 |
1 |
|
T1 |
9 |
|
T4 |
11 |
|
T21 |
1 |
| others[2] |
1183 |
1 |
|
T1 |
5 |
|
T4 |
19 |
|
T20 |
1 |
| others[3] |
2091 |
1 |
|
T1 |
24 |
|
T2 |
1 |
|
T4 |
37 |
| false |
669 |
1 |
|
T1 |
4 |
|
T4 |
16 |
|
T53 |
8 |
| true |
421 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T2 |
1 |
|
T222 |
1 |
|
T103 |
3 |
| others[1] |
124 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T391 |
1 |
| others[2] |
116 |
1 |
|
T21 |
1 |
|
T311 |
1 |
|
T183 |
1 |
| others[3] |
172 |
1 |
|
T21 |
2 |
|
T391 |
1 |
|
T393 |
1 |
| false |
53 |
1 |
|
T397 |
1 |
|
T103 |
3 |
|
T396 |
1 |
| true |
13518 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T63 |
1 |
|
T56 |
1 |
|
T200 |
1 |
| others[1] |
237 |
1 |
|
T183 |
1 |
|
T394 |
1 |
|
T274 |
1 |
| others[2] |
256 |
1 |
|
T23 |
1 |
|
T237 |
1 |
|
T391 |
1 |
| others[3] |
399 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T159 |
1 |
| false |
129 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T34 |
1 |
| true |
12847 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8302 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
11 |
| others[1] |
1019 |
1 |
|
T1 |
10 |
|
T4 |
7 |
|
T8 |
1 |
| others[2] |
1085 |
1 |
|
T1 |
2 |
|
T4 |
10 |
|
T6 |
1 |
| others[3] |
1751 |
1 |
|
T1 |
17 |
|
T2 |
1 |
|
T4 |
13 |
| false |
528 |
1 |
|
T1 |
7 |
|
T4 |
3 |
|
T53 |
5 |
| true |
1409 |
1 |
|
T4 |
56 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
2 |
| others[1] |
237 |
1 |
|
T31 |
1 |
|
T56 |
1 |
|
T393 |
1 |
| others[2] |
209 |
1 |
|
T2 |
1 |
|
T205 |
1 |
|
T394 |
1 |
| others[3] |
357 |
1 |
|
T20 |
1 |
|
T159 |
1 |
|
T35 |
1 |
| false |
133 |
1 |
|
T23 |
1 |
|
T48 |
1 |
|
T26 |
1 |
| true |
12908 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T188 |
1 |
|
T398 |
1 |
|
T103 |
11 |
| others[1] |
216 |
1 |
|
T57 |
1 |
|
T26 |
1 |
|
T246 |
1 |
| others[2] |
234 |
1 |
|
T21 |
2 |
|
T400 |
1 |
|
T395 |
1 |
| others[3] |
391 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T56 |
1 |
| false |
111 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T183 |
1 |
| true |
12941 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8471 |
1 |
|
T1 |
13 |
|
T4 |
19 |
|
T22 |
1 |
| others[1] |
1204 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
23 |
| others[2] |
1217 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
15 |
| others[3] |
2058 |
1 |
|
T1 |
10 |
|
T4 |
30 |
|
T58 |
1 |
| false |
692 |
1 |
|
T1 |
8 |
|
T4 |
13 |
|
T53 |
10 |
| true |
452 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
18 |
| others[1] |
1263 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
19 |
| others[2] |
1261 |
1 |
|
T1 |
11 |
|
T4 |
21 |
|
T8 |
1 |
| others[3] |
2013 |
1 |
|
T1 |
11 |
|
T4 |
31 |
|
T22 |
1 |
| false |
625 |
1 |
|
T1 |
5 |
|
T4 |
11 |
|
T64 |
1 |
| true |
425 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T21 |
1 |
|
T311 |
1 |
|
T183 |
1 |
| others[1] |
106 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T391 |
1 |
| others[2] |
102 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T394 |
1 |
| others[3] |
163 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T393 |
1 |
| false |
54 |
1 |
|
T95 |
1 |
|
T273 |
1 |
|
T103 |
2 |
| true |
6322 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T64 |
1 |
|
T24 |
1 |
|
T48 |
1 |
| others[1] |
246 |
1 |
|
T44 |
1 |
|
T57 |
1 |
|
T391 |
1 |
| others[2] |
248 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T26 |
1 |
| others[3] |
380 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T23 |
1 |
| false |
114 |
1 |
|
T398 |
1 |
|
T246 |
1 |
|
T403 |
1 |
| true |
5651 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
6 |
| others[1] |
1055 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
14 |
| others[2] |
1039 |
1 |
|
T1 |
7 |
|
T4 |
12 |
|
T18 |
1 |
| others[3] |
1757 |
1 |
|
T1 |
15 |
|
T4 |
11 |
|
T22 |
1 |
| false |
560 |
1 |
|
T1 |
3 |
|
T4 |
6 |
|
T21 |
1 |
| true |
1381 |
1 |
|
T4 |
51 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T43 |
1 |
|
T71 |
1 |
|
T246 |
1 |
| others[1] |
209 |
1 |
|
T23 |
1 |
|
T393 |
1 |
|
T395 |
1 |
| others[2] |
237 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| others[3] |
409 |
1 |
|
T5 |
1 |
|
T21 |
1 |
|
T391 |
1 |
| false |
135 |
1 |
|
T21 |
1 |
|
T64 |
1 |
|
T29 |
1 |
| true |
5630 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T2 |
1 |
|
T394 |
1 |
|
T103 |
6 |
| others[1] |
199 |
1 |
|
T311 |
1 |
|
T395 |
1 |
|
T103 |
9 |
| others[2] |
229 |
1 |
|
T391 |
1 |
|
T26 |
1 |
|
T103 |
14 |
| others[3] |
371 |
1 |
|
T33 |
1 |
|
T159 |
1 |
|
T391 |
1 |
| false |
118 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T95 |
1 |
| true |
5709 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1178 |
1 |
|
T1 |
8 |
|
T4 |
16 |
|
T21 |
3 |
| others[1] |
1246 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T4 |
20 |
| others[2] |
1231 |
1 |
|
T1 |
11 |
|
T4 |
17 |
|
T22 |
1 |
| others[3] |
2127 |
1 |
|
T1 |
17 |
|
T2 |
1 |
|
T4 |
36 |
| false |
632 |
1 |
|
T1 |
2 |
|
T4 |
11 |
|
T21 |
1 |
| true |
443 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T1 |
10 |
|
T4 |
15 |
|
T21 |
3 |
| others[1] |
1212 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
21 |
| others[2] |
1262 |
1 |
|
T1 |
11 |
|
T4 |
16 |
|
T18 |
1 |
| others[3] |
2048 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T4 |
39 |
| false |
638 |
1 |
|
T1 |
6 |
|
T4 |
9 |
|
T22 |
1 |
| true |
427 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T391 |
1 |
|
T95 |
1 |
|
T394 |
1 |
| others[1] |
109 |
1 |
|
T2 |
1 |
|
T239 |
1 |
|
T392 |
1 |
| others[2] |
99 |
1 |
|
T21 |
2 |
|
T393 |
1 |
|
T183 |
1 |
| others[3] |
180 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| false |
45 |
1 |
|
T21 |
1 |
|
T34 |
1 |
|
T103 |
1 |
| true |
6325 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T24 |
1 |
|
T188 |
1 |
|
T273 |
1 |
| others[1] |
222 |
1 |
|
T20 |
1 |
|
T101 |
1 |
|
T200 |
1 |
| others[2] |
244 |
1 |
|
T278 |
1 |
|
T36 |
1 |
|
T391 |
1 |
| others[3] |
398 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T48 |
1 |
| false |
116 |
1 |
|
T70 |
1 |
|
T401 |
1 |
|
T392 |
1 |
| true |
5650 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1089 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
10 |
| others[1] |
1031 |
1 |
|
T1 |
12 |
|
T4 |
6 |
|
T12 |
1 |
| others[2] |
1064 |
1 |
|
T1 |
9 |
|
T4 |
12 |
|
T21 |
3 |
| others[3] |
1706 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
11 |
| false |
562 |
1 |
|
T1 |
7 |
|
T4 |
6 |
|
T21 |
1 |
| true |
1405 |
1 |
|
T4 |
55 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T2 |
1 |
|
T159 |
1 |
|
T237 |
1 |
| others[1] |
210 |
1 |
|
T222 |
1 |
|
T402 |
1 |
|
T103 |
9 |
| others[2] |
235 |
1 |
|
T33 |
1 |
|
T29 |
1 |
|
T200 |
1 |
| others[3] |
372 |
1 |
|
T5 |
1 |
|
T64 |
1 |
|
T48 |
1 |
| false |
122 |
1 |
|
T183 |
1 |
|
T273 |
1 |
|
T71 |
1 |
| true |
5668 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
191 |
1 |
|
T43 |
1 |
|
T35 |
1 |
|
T273 |
1 |
| others[1] |
227 |
1 |
|
T57 |
1 |
|
T311 |
1 |
|
T26 |
1 |
| others[2] |
235 |
1 |
|
T397 |
1 |
|
T103 |
10 |
|
T396 |
2 |
| others[3] |
373 |
1 |
|
T2 |
1 |
|
T391 |
2 |
|
T95 |
1 |
| false |
109 |
1 |
|
T21 |
1 |
|
T103 |
3 |
|
T104 |
3 |
| true |
5722 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T1 |
11 |
|
T4 |
18 |
|
T21 |
1 |
| others[1] |
1262 |
1 |
|
T1 |
8 |
|
T4 |
21 |
|
T8 |
1 |
| others[2] |
1203 |
1 |
|
T1 |
7 |
|
T4 |
12 |
|
T21 |
1 |
| others[3] |
2107 |
1 |
|
T1 |
15 |
|
T2 |
2 |
|
T4 |
40 |
| false |
637 |
1 |
|
T1 |
6 |
|
T4 |
9 |
|
T22 |
1 |
| true |
433 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
16 |
| others[1] |
1242 |
1 |
|
T1 |
16 |
|
T4 |
23 |
|
T21 |
1 |
| others[2] |
1293 |
1 |
|
T1 |
5 |
|
T4 |
22 |
|
T53 |
26 |
| others[3] |
2022 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
34 |
| false |
622 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T22 |
1 |
| true |
425 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T34 |
1 |
|
T394 |
1 |
|
T103 |
5 |
| others[1] |
94 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T391 |
1 |
| others[2] |
104 |
1 |
|
T21 |
3 |
|
T393 |
1 |
|
T311 |
1 |
| others[3] |
184 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T391 |
1 |
| false |
56 |
1 |
|
T393 |
1 |
|
T394 |
1 |
|
T103 |
3 |
| true |
6327 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T5 |
1 |
|
T21 |
1 |
|
T183 |
1 |
| others[1] |
247 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T21 |
1 |
| others[2] |
214 |
1 |
|
T31 |
1 |
|
T43 |
1 |
|
T44 |
1 |
| others[3] |
402 |
1 |
|
T21 |
1 |
|
T64 |
1 |
|
T48 |
1 |
| false |
115 |
1 |
|
T34 |
1 |
|
T56 |
1 |
|
T222 |
1 |
| true |
5650 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T4 |
11 |
| others[1] |
1074 |
1 |
|
T1 |
9 |
|
T4 |
10 |
|
T6 |
1 |
| others[2] |
992 |
1 |
|
T1 |
10 |
|
T4 |
8 |
|
T21 |
1 |
| others[3] |
1815 |
1 |
|
T1 |
20 |
|
T2 |
1 |
|
T4 |
16 |
| false |
553 |
1 |
|
T1 |
4 |
|
T4 |
4 |
|
T8 |
1 |
| true |
1379 |
1 |
|
T4 |
51 |
|
T12 |
1 |
|
T59 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T63 |
1 |
| others[1] |
235 |
1 |
|
T32 |
1 |
|
T393 |
1 |
|
T70 |
1 |
| others[2] |
235 |
1 |
|
T21 |
1 |
|
T31 |
1 |
|
T159 |
1 |
| others[3] |
374 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T183 |
1 |
| false |
117 |
1 |
|
T20 |
1 |
|
T48 |
1 |
|
T391 |
1 |
| true |
5685 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T34 |
1 |
|
T394 |
1 |
|
T397 |
1 |
| others[1] |
254 |
1 |
|
T391 |
1 |
|
T183 |
1 |
|
T273 |
1 |
| others[2] |
205 |
1 |
|
T43 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| others[3] |
366 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T159 |
1 |
| false |
113 |
1 |
|
T56 |
1 |
|
T95 |
1 |
|
T103 |
8 |
| true |
5701 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T1 |
11 |
|
T4 |
27 |
|
T58 |
1 |
| others[1] |
1251 |
1 |
|
T1 |
7 |
|
T2 |
2 |
|
T4 |
18 |
| others[2] |
1223 |
1 |
|
T1 |
10 |
|
T4 |
19 |
|
T22 |
1 |
| others[3] |
2073 |
1 |
|
T1 |
15 |
|
T4 |
27 |
|
T21 |
1 |
| false |
631 |
1 |
|
T1 |
4 |
|
T4 |
9 |
|
T53 |
6 |
| true |
429 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |