Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1296 |
1 |
|
T1 |
14 |
|
T2 |
2 |
|
T4 |
18 |
| others[1] |
1241 |
1 |
|
T1 |
11 |
|
T4 |
19 |
|
T21 |
1 |
| others[2] |
1242 |
1 |
|
T1 |
8 |
|
T4 |
18 |
|
T8 |
1 |
| others[3] |
2035 |
1 |
|
T1 |
11 |
|
T4 |
36 |
|
T20 |
1 |
| false |
617 |
1 |
|
T1 |
3 |
|
T4 |
9 |
|
T58 |
1 |
| true |
426 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T2 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| others[1] |
111 |
1 |
|
T21 |
3 |
|
T183 |
1 |
|
T392 |
1 |
| others[2] |
115 |
1 |
|
T391 |
1 |
|
T393 |
1 |
|
T400 |
1 |
| others[3] |
176 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T34 |
1 |
| false |
53 |
1 |
|
T398 |
1 |
|
T103 |
3 |
|
T104 |
4 |
| true |
6298 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T35 |
1 |
| others[1] |
227 |
1 |
|
T21 |
1 |
|
T34 |
1 |
|
T246 |
1 |
| others[2] |
235 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T393 |
2 |
| others[3] |
406 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T31 |
1 |
| false |
111 |
1 |
|
T200 |
1 |
|
T404 |
1 |
|
T103 |
5 |
| true |
5630 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T1 |
8 |
|
T4 |
6 |
|
T22 |
1 |
| others[1] |
1077 |
1 |
|
T1 |
14 |
|
T4 |
11 |
|
T53 |
4 |
| others[2] |
1073 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
10 |
| others[3] |
1717 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
17 |
| false |
522 |
1 |
|
T1 |
5 |
|
T4 |
4 |
|
T6 |
1 |
| true |
1400 |
1 |
|
T4 |
52 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T23 |
1 |
|
T48 |
1 |
|
T70 |
1 |
| others[1] |
238 |
1 |
|
T64 |
1 |
|
T31 |
1 |
|
T32 |
1 |
| others[2] |
217 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T183 |
1 |
| others[3] |
384 |
1 |
|
T5 |
1 |
|
T237 |
1 |
|
T311 |
1 |
| false |
114 |
1 |
|
T159 |
1 |
|
T405 |
1 |
|
T274 |
1 |
| true |
5677 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T35 |
1 |
|
T26 |
1 |
|
T103 |
9 |
| others[1] |
226 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T311 |
1 |
| others[2] |
209 |
1 |
|
T43 |
1 |
|
T395 |
1 |
|
T103 |
9 |
| others[3] |
396 |
1 |
|
T159 |
1 |
|
T34 |
1 |
|
T391 |
1 |
| false |
89 |
1 |
|
T18 |
1 |
|
T103 |
2 |
|
T104 |
8 |
| true |
5691 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
20 |
| others[1] |
1239 |
1 |
|
T1 |
10 |
|
T4 |
15 |
|
T53 |
14 |
| others[2] |
1230 |
1 |
|
T1 |
9 |
|
T4 |
21 |
|
T53 |
18 |
| others[3] |
2058 |
1 |
|
T1 |
17 |
|
T2 |
1 |
|
T4 |
36 |
| false |
619 |
1 |
|
T1 |
3 |
|
T4 |
8 |
|
T22 |
1 |
| true |
446 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1190 |
1 |
|
T1 |
14 |
|
T2 |
2 |
|
T4 |
19 |
| others[1] |
1229 |
1 |
|
T1 |
7 |
|
T4 |
21 |
|
T21 |
3 |
| others[2] |
1228 |
1 |
|
T1 |
7 |
|
T4 |
14 |
|
T53 |
17 |
| others[3] |
2128 |
1 |
|
T1 |
16 |
|
T4 |
39 |
|
T18 |
1 |
| false |
657 |
1 |
|
T1 |
3 |
|
T4 |
7 |
|
T22 |
1 |
| true |
425 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T21 |
2 |
|
T391 |
1 |
|
T273 |
1 |
| others[1] |
102 |
1 |
|
T393 |
1 |
|
T394 |
1 |
|
T392 |
1 |
| others[2] |
114 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T394 |
1 |
| others[3] |
157 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T35 |
1 |
| false |
65 |
1 |
|
T393 |
1 |
|
T311 |
1 |
|
T397 |
1 |
| true |
6304 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T20 |
1 |
|
T36 |
1 |
|
T205 |
1 |
| others[1] |
241 |
1 |
|
T33 |
1 |
|
T278 |
1 |
|
T44 |
1 |
| others[2] |
222 |
1 |
|
T2 |
1 |
|
T64 |
1 |
|
T101 |
1 |
| others[3] |
389 |
1 |
|
T21 |
1 |
|
T24 |
1 |
|
T32 |
1 |
| false |
126 |
1 |
|
T23 |
1 |
|
T43 |
1 |
|
T37 |
1 |
| true |
5635 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1081 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
11 |
| others[1] |
1090 |
1 |
|
T1 |
7 |
|
T4 |
7 |
|
T22 |
1 |
| others[2] |
1035 |
1 |
|
T1 |
14 |
|
T4 |
9 |
|
T33 |
1 |
| others[3] |
1738 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T4 |
9 |
| false |
562 |
1 |
|
T1 |
3 |
|
T4 |
5 |
|
T21 |
1 |
| true |
1351 |
1 |
|
T4 |
59 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T43 |
1 |
|
T29 |
1 |
|
T188 |
1 |
| others[1] |
225 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T32 |
1 |
| others[2] |
228 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T392 |
1 |
| others[3] |
402 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T21 |
1 |
| false |
96 |
1 |
|
T23 |
1 |
|
T71 |
1 |
|
T103 |
2 |
| true |
5658 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T246 |
2 |
|
T103 |
12 |
|
T81 |
1 |
| others[1] |
211 |
1 |
|
T18 |
1 |
|
T21 |
2 |
|
T397 |
1 |
| others[2] |
239 |
1 |
|
T21 |
1 |
|
T393 |
1 |
|
T183 |
1 |
| others[3] |
399 |
1 |
|
T56 |
1 |
|
T393 |
1 |
|
T95 |
1 |
| false |
111 |
1 |
|
T103 |
4 |
|
T104 |
5 |
|
T105 |
7 |
| true |
5654 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T1 |
9 |
|
T4 |
15 |
|
T53 |
15 |
| others[1] |
1211 |
1 |
|
T1 |
9 |
|
T4 |
18 |
|
T20 |
1 |
| others[2] |
1227 |
1 |
|
T1 |
9 |
|
T2 |
2 |
|
T4 |
19 |
| others[3] |
2091 |
1 |
|
T1 |
19 |
|
T4 |
40 |
|
T21 |
2 |
| false |
638 |
1 |
|
T1 |
1 |
|
T4 |
8 |
|
T22 |
1 |
| true |
434 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1184 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
16 |
| others[1] |
1249 |
1 |
|
T1 |
9 |
|
T4 |
16 |
|
T53 |
21 |
| others[2] |
1247 |
1 |
|
T1 |
11 |
|
T4 |
24 |
|
T21 |
1 |
| others[3] |
2138 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
31 |
| false |
622 |
1 |
|
T1 |
5 |
|
T4 |
13 |
|
T21 |
1 |
| true |
417 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T34 |
1 |
|
T222 |
1 |
|
T397 |
1 |
| others[1] |
90 |
1 |
|
T21 |
1 |
|
T26 |
1 |
|
T394 |
1 |
| others[2] |
116 |
1 |
|
T35 |
1 |
|
T391 |
2 |
|
T393 |
2 |
| others[3] |
186 |
1 |
|
T2 |
1 |
|
T21 |
3 |
|
T246 |
1 |
| false |
50 |
1 |
|
T2 |
1 |
|
T183 |
1 |
|
T394 |
1 |
| true |
6307 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| others[1] |
250 |
1 |
|
T35 |
1 |
|
T266 |
1 |
|
T401 |
1 |
| others[2] |
256 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T237 |
1 |
| others[3] |
378 |
1 |
|
T391 |
1 |
|
T393 |
1 |
|
T37 |
1 |
| false |
112 |
1 |
|
T21 |
1 |
|
T24 |
1 |
|
T43 |
1 |
| true |
5647 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1045 |
1 |
|
T1 |
9 |
|
T4 |
8 |
|
T5 |
1 |
| others[1] |
1081 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
13 |
| others[2] |
1040 |
1 |
|
T1 |
6 |
|
T4 |
11 |
|
T21 |
1 |
| others[3] |
1739 |
1 |
|
T1 |
16 |
|
T2 |
1 |
|
T4 |
17 |
| false |
564 |
1 |
|
T1 |
2 |
|
T4 |
7 |
|
T6 |
1 |
| true |
1388 |
1 |
|
T4 |
44 |
|
T12 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T21 |
1 |
|
T57 |
1 |
|
T103 |
10 |
| others[1] |
235 |
1 |
|
T23 |
1 |
|
T400 |
1 |
|
T398 |
1 |
| others[2] |
241 |
1 |
|
T21 |
1 |
|
T63 |
1 |
|
T393 |
1 |
| others[3] |
400 |
1 |
|
T5 |
1 |
|
T20 |
1 |
|
T21 |
1 |
| false |
123 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T35 |
1 |
| true |
5637 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T2 |
2 |
|
T183 |
1 |
|
T400 |
1 |
| others[1] |
245 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T103 |
8 |
| others[2] |
228 |
1 |
|
T64 |
1 |
|
T44 |
1 |
|
T35 |
1 |
| others[3] |
357 |
1 |
|
T34 |
1 |
|
T398 |
1 |
|
T246 |
1 |
| false |
125 |
1 |
|
T43 |
1 |
|
T311 |
1 |
|
T103 |
5 |
| true |
5686 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T1 |
13 |
|
T2 |
2 |
|
T4 |
20 |
| others[1] |
1251 |
1 |
|
T1 |
10 |
|
T4 |
17 |
|
T21 |
2 |
| others[2] |
1208 |
1 |
|
T1 |
6 |
|
T4 |
21 |
|
T59 |
1 |
| others[3] |
2089 |
1 |
|
T1 |
11 |
|
T4 |
35 |
|
T8 |
1 |
| false |
645 |
1 |
|
T1 |
7 |
|
T4 |
7 |
|
T21 |
1 |
| true |
442 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T1 |
9 |
|
T4 |
12 |
|
T22 |
1 |
| others[1] |
1228 |
1 |
|
T1 |
10 |
|
T4 |
27 |
|
T8 |
1 |
| others[2] |
1246 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
17 |
| others[3] |
2069 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
35 |
| false |
653 |
1 |
|
T1 |
2 |
|
T4 |
9 |
|
T53 |
10 |
| true |
421 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T159 |
1 |
| others[1] |
92 |
1 |
|
T393 |
1 |
|
T246 |
1 |
|
T392 |
1 |
| others[2] |
86 |
1 |
|
T21 |
1 |
|
T393 |
1 |
|
T394 |
2 |
| others[3] |
156 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T391 |
2 |
| false |
53 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T183 |
1 |
| true |
6359 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T20 |
1 |
|
T24 |
1 |
|
T35 |
1 |
| others[1] |
214 |
1 |
|
T48 |
1 |
|
T57 |
1 |
|
T311 |
1 |
| others[2] |
253 |
1 |
|
T18 |
1 |
|
T34 |
1 |
|
T183 |
1 |
| others[3] |
409 |
1 |
|
T2 |
1 |
|
T21 |
3 |
|
T33 |
1 |
| false |
107 |
1 |
|
T200 |
1 |
|
T274 |
1 |
|
T103 |
1 |
| true |
5648 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T1 |
10 |
|
T4 |
11 |
|
T12 |
1 |
| others[1] |
1025 |
1 |
|
T1 |
12 |
|
T4 |
8 |
|
T5 |
1 |
| others[2] |
1067 |
1 |
|
T1 |
4 |
|
T4 |
8 |
|
T58 |
1 |
| others[3] |
1741 |
1 |
|
T1 |
19 |
|
T2 |
2 |
|
T4 |
19 |
| false |
541 |
1 |
|
T1 |
2 |
|
T4 |
4 |
|
T53 |
3 |
| true |
1418 |
1 |
|
T4 |
50 |
|
T6 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T5 |
1 |
|
T21 |
1 |
|
T159 |
1 |
| others[1] |
228 |
1 |
|
T393 |
1 |
|
T183 |
1 |
|
T272 |
1 |
| others[2] |
222 |
1 |
|
T64 |
1 |
|
T48 |
1 |
|
T44 |
1 |
| others[3] |
387 |
1 |
|
T33 |
1 |
|
T31 |
1 |
|
T43 |
1 |
| false |
113 |
1 |
|
T21 |
1 |
|
T32 |
1 |
|
T246 |
1 |
| true |
5696 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T44 |
1 |
|
T26 |
1 |
|
T103 |
5 |
| others[1] |
213 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| others[2] |
203 |
1 |
|
T64 |
1 |
|
T57 |
1 |
|
T395 |
1 |
| others[3] |
373 |
1 |
|
T21 |
1 |
|
T35 |
1 |
|
T273 |
1 |
| false |
98 |
1 |
|
T43 |
1 |
|
T95 |
1 |
|
T394 |
1 |
| true |
5766 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T4 |
19 |
| others[1] |
1234 |
1 |
|
T1 |
9 |
|
T4 |
19 |
|
T22 |
1 |
| others[2] |
1252 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T4 |
23 |
| others[3] |
2073 |
1 |
|
T1 |
12 |
|
T4 |
33 |
|
T18 |
1 |
| false |
646 |
1 |
|
T1 |
2 |
|
T4 |
6 |
|
T58 |
1 |
| true |
432 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1210 |
1 |
|
T1 |
9 |
|
T4 |
22 |
|
T22 |
1 |
| others[1] |
1244 |
1 |
|
T1 |
11 |
|
T4 |
16 |
|
T53 |
16 |
| others[2] |
1214 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
17 |
| others[3] |
2170 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
30 |
| false |
591 |
1 |
|
T1 |
3 |
|
T4 |
15 |
|
T21 |
1 |
| true |
428 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T183 |
1 |
|
T401 |
1 |
|
T394 |
1 |
| others[1] |
101 |
1 |
|
T391 |
1 |
|
T393 |
2 |
|
T70 |
1 |
| others[2] |
96 |
1 |
|
T21 |
1 |
|
T159 |
1 |
|
T95 |
1 |
| others[3] |
156 |
1 |
|
T2 |
1 |
|
T21 |
2 |
|
T56 |
1 |
| false |
54 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T103 |
3 |
| true |
6347 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T393 |
1 |
|
T185 |
1 |
|
T30 |
1 |
| others[1] |
248 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T159 |
1 |
| others[2] |
241 |
1 |
|
T24 |
1 |
|
T32 |
1 |
|
T203 |
1 |
| others[3] |
388 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T18 |
1 |
| false |
123 |
1 |
|
T21 |
1 |
|
T95 |
1 |
|
T246 |
1 |
| true |
5609 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |