Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1085 |
1 |
|
T1 |
12 |
|
T4 |
11 |
|
T20 |
1 |
| others[1] |
1104 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T4 |
12 |
| others[2] |
999 |
1 |
|
T1 |
2 |
|
T4 |
5 |
|
T6 |
1 |
| others[3] |
1784 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
12 |
| false |
545 |
1 |
|
T1 |
8 |
|
T4 |
9 |
|
T21 |
1 |
| true |
1340 |
1 |
|
T4 |
51 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T311 |
1 |
| others[1] |
261 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T43 |
1 |
| others[2] |
242 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T64 |
1 |
| others[3] |
394 |
1 |
|
T393 |
1 |
|
T95 |
1 |
|
T188 |
1 |
| false |
119 |
1 |
|
T48 |
1 |
|
T63 |
1 |
|
T103 |
9 |
| true |
5612 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T21 |
1 |
|
T57 |
1 |
|
T26 |
1 |
| others[1] |
205 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
2 |
| others[2] |
222 |
1 |
|
T2 |
1 |
|
T64 |
1 |
|
T43 |
1 |
| others[3] |
381 |
1 |
|
T21 |
1 |
|
T159 |
1 |
|
T34 |
1 |
| false |
107 |
1 |
|
T393 |
1 |
|
T246 |
1 |
|
T103 |
2 |
| true |
5702 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
16 |
| others[1] |
1215 |
1 |
|
T1 |
8 |
|
T4 |
16 |
|
T58 |
1 |
| others[2] |
1238 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
27 |
| others[3] |
2086 |
1 |
|
T1 |
13 |
|
T4 |
32 |
|
T21 |
1 |
| false |
637 |
1 |
|
T1 |
3 |
|
T4 |
9 |
|
T21 |
1 |
| true |
452 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1301 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T4 |
26 |
| others[1] |
1193 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
12 |
| others[2] |
1261 |
1 |
|
T1 |
11 |
|
T4 |
18 |
|
T21 |
1 |
| others[3] |
2042 |
1 |
|
T1 |
18 |
|
T4 |
34 |
|
T59 |
1 |
| false |
642 |
1 |
|
T1 |
4 |
|
T4 |
10 |
|
T22 |
1 |
| true |
418 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T2 |
2 |
|
T393 |
1 |
|
T311 |
1 |
| others[1] |
100 |
1 |
|
T34 |
1 |
|
T398 |
1 |
|
T397 |
2 |
| others[2] |
102 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T183 |
1 |
| others[3] |
179 |
1 |
|
T21 |
2 |
|
T391 |
1 |
|
T393 |
1 |
| false |
57 |
1 |
|
T21 |
1 |
|
T70 |
1 |
|
T394 |
1 |
| true |
6325 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T18 |
1 |
|
T32 |
1 |
|
T278 |
1 |
| others[1] |
226 |
1 |
|
T5 |
1 |
|
T21 |
2 |
|
T24 |
1 |
| others[2] |
227 |
1 |
|
T2 |
1 |
|
T21 |
2 |
|
T48 |
1 |
| others[3] |
397 |
1 |
|
T64 |
1 |
|
T57 |
1 |
|
T391 |
1 |
| false |
130 |
1 |
|
T37 |
1 |
|
T273 |
1 |
|
T392 |
1 |
| true |
5664 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T1 |
15 |
|
T4 |
10 |
|
T5 |
1 |
| others[1] |
1076 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
9 |
| others[2] |
1071 |
1 |
|
T1 |
6 |
|
T4 |
10 |
|
T7 |
1 |
| others[3] |
1747 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T4 |
13 |
| false |
507 |
1 |
|
T1 |
1 |
|
T4 |
3 |
|
T8 |
1 |
| true |
1386 |
1 |
|
T4 |
55 |
|
T18 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T64 |
1 |
|
T48 |
1 |
|
T43 |
1 |
| others[1] |
242 |
1 |
|
T29 |
1 |
|
T200 |
1 |
|
T266 |
1 |
| others[2] |
243 |
1 |
|
T34 |
1 |
|
T203 |
1 |
|
T26 |
1 |
| others[3] |
363 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| false |
121 |
1 |
|
T33 |
1 |
|
T404 |
1 |
|
T103 |
6 |
| true |
5658 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T21 |
1 |
|
T35 |
1 |
|
T391 |
1 |
| others[1] |
236 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| others[2] |
207 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T64 |
1 |
| others[3] |
357 |
1 |
|
T311 |
1 |
|
T398 |
1 |
|
T246 |
1 |
| false |
108 |
1 |
|
T103 |
2 |
|
T104 |
1 |
|
T105 |
6 |
| true |
5723 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T1 |
6 |
|
T4 |
20 |
|
T53 |
17 |
| others[1] |
1219 |
1 |
|
T1 |
10 |
|
T4 |
17 |
|
T8 |
1 |
| others[2] |
1276 |
1 |
|
T1 |
10 |
|
T4 |
22 |
|
T21 |
1 |
| others[3] |
2008 |
1 |
|
T1 |
18 |
|
T2 |
2 |
|
T4 |
27 |
| false |
655 |
1 |
|
T1 |
3 |
|
T4 |
14 |
|
T22 |
1 |
| true |
442 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T1 |
8 |
|
T4 |
14 |
|
T58 |
1 |
| others[1] |
1199 |
1 |
|
T1 |
8 |
|
T4 |
17 |
|
T8 |
1 |
| others[2] |
1230 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
20 |
| others[3] |
2118 |
1 |
|
T1 |
14 |
|
T4 |
41 |
|
T22 |
1 |
| false |
646 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
8 |
| true |
433 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T70 |
1 |
| others[1] |
101 |
1 |
|
T2 |
1 |
|
T21 |
2 |
|
T393 |
2 |
| others[2] |
106 |
1 |
|
T21 |
1 |
|
T35 |
1 |
|
T222 |
1 |
| others[3] |
181 |
1 |
|
T2 |
1 |
|
T183 |
1 |
|
T398 |
1 |
| false |
49 |
1 |
|
T18 |
1 |
|
T391 |
1 |
|
T311 |
1 |
| true |
6313 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T237 |
1 |
|
T393 |
1 |
|
T185 |
1 |
| others[1] |
211 |
1 |
|
T23 |
1 |
|
T31 |
1 |
|
T34 |
1 |
| others[2] |
219 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T35 |
1 |
| others[3] |
375 |
1 |
|
T2 |
1 |
|
T21 |
2 |
|
T24 |
1 |
| false |
131 |
1 |
|
T20 |
1 |
|
T48 |
1 |
|
T159 |
1 |
| true |
5670 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
7 |
| others[1] |
1095 |
1 |
|
T1 |
13 |
|
T4 |
13 |
|
T5 |
1 |
| others[2] |
1068 |
1 |
|
T1 |
8 |
|
T4 |
8 |
|
T12 |
1 |
| others[3] |
1709 |
1 |
|
T1 |
16 |
|
T2 |
1 |
|
T4 |
19 |
| false |
518 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T21 |
1 |
| true |
1399 |
1 |
|
T4 |
50 |
|
T6 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T48 |
1 |
|
T401 |
1 |
|
T246 |
1 |
| others[1] |
207 |
1 |
|
T2 |
1 |
|
T64 |
1 |
|
T56 |
1 |
| others[2] |
240 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T35 |
1 |
| others[3] |
371 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T31 |
1 |
| false |
140 |
1 |
|
T63 |
1 |
|
T32 |
1 |
|
T393 |
1 |
| true |
5650 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T311 |
1 |
|
T188 |
1 |
|
T397 |
1 |
| others[1] |
244 |
1 |
|
T21 |
1 |
|
T64 |
1 |
|
T159 |
1 |
| others[2] |
190 |
1 |
|
T34 |
1 |
|
T393 |
1 |
|
T103 |
8 |
| others[3] |
381 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T43 |
1 |
| false |
117 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T398 |
1 |
| true |
5701 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1280 |
1 |
|
T1 |
6 |
|
T4 |
19 |
|
T22 |
1 |
| others[1] |
1289 |
1 |
|
T1 |
14 |
|
T4 |
22 |
|
T53 |
21 |
| others[2] |
1227 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
19 |
| others[3] |
1980 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T4 |
35 |
| false |
651 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T53 |
15 |
| true |
430 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1174 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T4 |
18 |
| others[1] |
1190 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T4 |
19 |
| others[2] |
1282 |
1 |
|
T1 |
9 |
|
T4 |
19 |
|
T22 |
1 |
| others[3] |
2159 |
1 |
|
T1 |
13 |
|
T4 |
36 |
|
T18 |
1 |
| false |
639 |
1 |
|
T1 |
4 |
|
T4 |
8 |
|
T21 |
1 |
| true |
413 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T394 |
1 |
|
T392 |
1 |
|
T103 |
8 |
| others[1] |
100 |
1 |
|
T21 |
1 |
|
T57 |
1 |
|
T397 |
2 |
| others[2] |
95 |
1 |
|
T2 |
1 |
|
T391 |
1 |
|
T311 |
1 |
| others[3] |
183 |
1 |
|
T2 |
1 |
|
T21 |
3 |
|
T34 |
1 |
| false |
50 |
1 |
|
T398 |
1 |
|
T103 |
4 |
|
T104 |
2 |
| true |
6328 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
275 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T64 |
1 |
| others[1] |
214 |
1 |
|
T23 |
1 |
|
T391 |
1 |
|
T205 |
1 |
| others[2] |
244 |
1 |
|
T5 |
1 |
|
T278 |
1 |
|
T203 |
1 |
| others[3] |
410 |
1 |
|
T21 |
2 |
|
T33 |
1 |
|
T159 |
1 |
| false |
109 |
1 |
|
T48 |
1 |
|
T403 |
1 |
|
T392 |
1 |
| true |
5605 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1087 |
1 |
|
T1 |
7 |
|
T4 |
6 |
|
T5 |
1 |
| others[1] |
1005 |
1 |
|
T1 |
6 |
|
T4 |
9 |
|
T18 |
1 |
| others[2] |
1040 |
1 |
|
T1 |
11 |
|
T2 |
2 |
|
T4 |
7 |
| others[3] |
1736 |
1 |
|
T1 |
17 |
|
T4 |
13 |
|
T8 |
1 |
| false |
574 |
1 |
|
T1 |
6 |
|
T4 |
6 |
|
T21 |
1 |
| true |
1415 |
1 |
|
T4 |
59 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T48 |
1 |
| others[1] |
228 |
1 |
|
T56 |
1 |
|
T30 |
1 |
|
T246 |
1 |
| others[2] |
241 |
1 |
|
T183 |
1 |
|
T403 |
1 |
|
T404 |
1 |
| others[3] |
384 |
1 |
|
T57 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| false |
110 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T95 |
1 |
| true |
5683 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T18 |
1 |
|
T33 |
1 |
|
T392 |
1 |
| others[1] |
229 |
1 |
|
T57 |
1 |
|
T95 |
1 |
|
T26 |
1 |
| others[2] |
209 |
1 |
|
T159 |
1 |
|
T56 |
1 |
|
T70 |
1 |
| others[3] |
347 |
1 |
|
T2 |
1 |
|
T64 |
1 |
|
T34 |
1 |
| false |
111 |
1 |
|
T21 |
1 |
|
T43 |
1 |
|
T393 |
1 |
| true |
5749 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1193 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
22 |
| others[1] |
1281 |
1 |
|
T1 |
9 |
|
T4 |
32 |
|
T22 |
1 |
| others[2] |
1241 |
1 |
|
T1 |
9 |
|
T4 |
21 |
|
T53 |
28 |
| others[3] |
2037 |
1 |
|
T1 |
18 |
|
T4 |
15 |
|
T20 |
1 |
| false |
654 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
10 |
| true |
451 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T1 |
12 |
|
T4 |
21 |
|
T8 |
1 |
| others[1] |
1251 |
1 |
|
T1 |
9 |
|
T4 |
25 |
|
T53 |
21 |
| others[2] |
1224 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
16 |
| others[3] |
2036 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
30 |
| false |
649 |
1 |
|
T1 |
2 |
|
T4 |
8 |
|
T21 |
1 |
| true |
431 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T21 |
1 |
|
T394 |
1 |
|
T397 |
1 |
| others[1] |
95 |
1 |
|
T2 |
2 |
|
T56 |
1 |
|
T311 |
1 |
| others[2] |
107 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| others[3] |
184 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| false |
51 |
1 |
|
T21 |
1 |
|
T239 |
1 |
|
T103 |
1 |
| true |
6324 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T18 |
1 |
|
T48 |
1 |
|
T63 |
1 |
| others[1] |
214 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T391 |
1 |
| others[2] |
261 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T394 |
1 |
| others[3] |
358 |
1 |
|
T24 |
1 |
|
T31 |
1 |
|
T159 |
1 |
| false |
132 |
1 |
|
T21 |
2 |
|
T23 |
1 |
|
T237 |
1 |
| true |
5642 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T1 |
5 |
|
T4 |
8 |
|
T12 |
1 |
| others[1] |
1027 |
1 |
|
T1 |
6 |
|
T2 |
2 |
|
T4 |
6 |
| others[2] |
1034 |
1 |
|
T1 |
11 |
|
T4 |
9 |
|
T18 |
1 |
| others[3] |
1753 |
1 |
|
T1 |
18 |
|
T4 |
13 |
|
T21 |
2 |
| false |
558 |
1 |
|
T1 |
7 |
|
T4 |
9 |
|
T22 |
1 |
| true |
1415 |
1 |
|
T4 |
55 |
|
T33 |
1 |
|
T59 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T57 |
1 |
|
T393 |
1 |
|
T95 |
1 |
| others[1] |
230 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T103 |
12 |
| others[2] |
216 |
1 |
|
T159 |
1 |
|
T56 |
1 |
|
T401 |
1 |
| others[3] |
372 |
1 |
|
T33 |
1 |
|
T23 |
1 |
|
T48 |
1 |
| false |
125 |
1 |
|
T5 |
1 |
|
T21 |
1 |
|
T35 |
1 |
| true |
5666 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T2 |
1 |
|
T393 |
1 |
|
T183 |
1 |
| others[1] |
206 |
1 |
|
T64 |
1 |
|
T95 |
1 |
|
T70 |
1 |
| others[2] |
213 |
1 |
|
T21 |
1 |
|
T159 |
1 |
|
T395 |
1 |
| others[3] |
353 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| false |
125 |
1 |
|
T21 |
1 |
|
T56 |
1 |
|
T391 |
1 |
| true |
5743 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |