Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T1 |
6 |
|
T4 |
23 |
|
T8 |
1 |
| others[1] |
1254 |
1 |
|
T1 |
16 |
|
T2 |
1 |
|
T4 |
21 |
| others[2] |
1210 |
1 |
|
T1 |
8 |
|
T4 |
14 |
|
T21 |
1 |
| others[3] |
2138 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
29 |
| false |
624 |
1 |
|
T1 |
3 |
|
T4 |
13 |
|
T5 |
1 |
| true |
424 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T1 |
5 |
|
T4 |
20 |
|
T8 |
1 |
| others[1] |
1255 |
1 |
|
T1 |
9 |
|
T4 |
25 |
|
T21 |
2 |
| others[2] |
1215 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
20 |
| others[3] |
2079 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
30 |
| false |
658 |
1 |
|
T1 |
5 |
|
T4 |
5 |
|
T21 |
1 |
| true |
422 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T21 |
3 |
|
T56 |
1 |
|
T391 |
1 |
| others[1] |
101 |
1 |
|
T393 |
1 |
|
T311 |
1 |
|
T273 |
1 |
| others[2] |
95 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T391 |
1 |
| others[3] |
202 |
1 |
|
T2 |
1 |
|
T183 |
1 |
|
T95 |
1 |
| false |
60 |
1 |
|
T103 |
4 |
|
T104 |
1 |
|
T105 |
2 |
| true |
6284 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
268 |
1 |
|
T2 |
1 |
|
T57 |
1 |
|
T95 |
1 |
| others[1] |
224 |
1 |
|
T21 |
1 |
|
T48 |
1 |
|
T393 |
1 |
| others[2] |
231 |
1 |
|
T159 |
1 |
|
T37 |
1 |
|
T26 |
1 |
| others[3] |
401 |
1 |
|
T33 |
1 |
|
T64 |
1 |
|
T34 |
1 |
| false |
114 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T21 |
2 |
| true |
5619 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1050 |
1 |
|
T1 |
8 |
|
T4 |
14 |
|
T53 |
14 |
| others[1] |
1030 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
7 |
| others[2] |
1062 |
1 |
|
T1 |
11 |
|
T4 |
12 |
|
T8 |
1 |
| others[3] |
1747 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
16 |
| false |
576 |
1 |
|
T1 |
4 |
|
T4 |
4 |
|
T5 |
1 |
| true |
1392 |
1 |
|
T4 |
47 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T2 |
1 |
|
T21 |
2 |
|
T31 |
1 |
| others[1] |
210 |
1 |
|
T21 |
1 |
|
T63 |
1 |
|
T393 |
1 |
| others[2] |
259 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T64 |
1 |
| others[3] |
362 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T183 |
1 |
| false |
138 |
1 |
|
T34 |
1 |
|
T71 |
1 |
|
T398 |
1 |
| true |
5646 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
185 |
1 |
|
T35 |
1 |
|
T311 |
1 |
|
T246 |
2 |
| others[1] |
229 |
1 |
|
T18 |
1 |
|
T64 |
1 |
|
T34 |
1 |
| others[2] |
239 |
1 |
|
T21 |
1 |
|
T57 |
1 |
|
T401 |
1 |
| others[3] |
357 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| false |
136 |
1 |
|
T21 |
1 |
|
T103 |
10 |
|
T104 |
7 |
| true |
5711 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
22 |
| others[1] |
1236 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
19 |
| others[2] |
1236 |
1 |
|
T1 |
12 |
|
T4 |
17 |
|
T20 |
1 |
| others[3] |
2053 |
1 |
|
T1 |
10 |
|
T4 |
29 |
|
T22 |
1 |
| false |
645 |
1 |
|
T1 |
7 |
|
T4 |
13 |
|
T53 |
12 |
| true |
435 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T1 |
5 |
|
T4 |
22 |
|
T22 |
1 |
| others[1] |
1269 |
1 |
|
T1 |
10 |
|
T4 |
22 |
|
T21 |
2 |
| others[2] |
1238 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
21 |
| others[3] |
2013 |
1 |
|
T1 |
13 |
|
T2 |
1 |
|
T4 |
29 |
| false |
628 |
1 |
|
T1 |
5 |
|
T4 |
6 |
|
T8 |
1 |
| true |
427 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T246 |
1 |
|
T397 |
1 |
|
T392 |
1 |
| others[1] |
120 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| others[2] |
94 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T393 |
1 |
| others[3] |
169 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
2 |
| false |
48 |
1 |
|
T103 |
2 |
|
T396 |
1 |
|
T104 |
3 |
| true |
6330 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T311 |
1 |
| others[1] |
253 |
1 |
|
T64 |
1 |
|
T32 |
1 |
|
T37 |
1 |
| others[2] |
216 |
1 |
|
T31 |
1 |
|
T43 |
1 |
|
T56 |
1 |
| others[3] |
407 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T21 |
2 |
| false |
119 |
1 |
|
T5 |
1 |
|
T393 |
1 |
|
T188 |
1 |
| true |
5609 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T1 |
11 |
|
T2 |
2 |
|
T4 |
6 |
| others[1] |
1055 |
1 |
|
T1 |
10 |
|
T4 |
6 |
|
T8 |
1 |
| others[2] |
1013 |
1 |
|
T1 |
9 |
|
T4 |
9 |
|
T21 |
1 |
| others[3] |
1795 |
1 |
|
T1 |
12 |
|
T4 |
12 |
|
T12 |
1 |
| false |
585 |
1 |
|
T1 |
5 |
|
T4 |
7 |
|
T21 |
1 |
| true |
1391 |
1 |
|
T4 |
60 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T43 |
1 |
|
T393 |
1 |
|
T203 |
1 |
| others[1] |
229 |
1 |
|
T21 |
1 |
|
T48 |
1 |
|
T159 |
1 |
| others[2] |
239 |
1 |
|
T35 |
1 |
|
T26 |
1 |
|
T394 |
1 |
| others[3] |
380 |
1 |
|
T21 |
1 |
|
T64 |
1 |
|
T34 |
1 |
| false |
114 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T103 |
10 |
| true |
5649 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T401 |
1 |
|
T71 |
1 |
|
T246 |
1 |
| others[1] |
233 |
1 |
|
T395 |
1 |
|
T246 |
2 |
|
T397 |
1 |
| others[2] |
212 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T44 |
1 |
| others[3] |
359 |
1 |
|
T21 |
1 |
|
T43 |
1 |
|
T400 |
1 |
| false |
104 |
1 |
|
T21 |
1 |
|
T56 |
1 |
|
T95 |
1 |
| true |
5732 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T1 |
10 |
|
T4 |
23 |
|
T21 |
1 |
| others[1] |
1191 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
14 |
| others[2] |
1232 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
19 |
| others[3] |
2070 |
1 |
|
T1 |
22 |
|
T4 |
32 |
|
T21 |
1 |
| false |
664 |
1 |
|
T1 |
2 |
|
T4 |
12 |
|
T18 |
1 |
| true |
438 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
22 |
| others[1] |
1214 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
24 |
| others[2] |
1195 |
1 |
|
T1 |
7 |
|
T4 |
11 |
|
T21 |
1 |
| others[3] |
2117 |
1 |
|
T1 |
14 |
|
T4 |
32 |
|
T21 |
2 |
| false |
661 |
1 |
|
T1 |
6 |
|
T4 |
11 |
|
T21 |
1 |
| true |
430 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T21 |
1 |
|
T43 |
1 |
|
T394 |
2 |
| others[1] |
106 |
1 |
|
T21 |
2 |
|
T391 |
1 |
|
T393 |
1 |
| others[2] |
106 |
1 |
|
T21 |
1 |
|
T400 |
1 |
|
T246 |
1 |
| others[3] |
185 |
1 |
|
T18 |
1 |
|
T33 |
1 |
|
T391 |
1 |
| false |
47 |
1 |
|
T2 |
2 |
|
T393 |
1 |
|
T103 |
6 |
| true |
6317 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T30 |
1 |
|
T246 |
1 |
|
T392 |
1 |
| others[1] |
219 |
1 |
|
T34 |
1 |
|
T32 |
1 |
|
T95 |
1 |
| others[2] |
242 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T63 |
1 |
| others[3] |
406 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| false |
122 |
1 |
|
T5 |
1 |
|
T31 |
1 |
|
T405 |
1 |
| true |
5608 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1055 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
10 |
| others[1] |
1065 |
1 |
|
T1 |
8 |
|
T4 |
9 |
|
T21 |
1 |
| others[2] |
1041 |
1 |
|
T1 |
8 |
|
T4 |
4 |
|
T21 |
2 |
| others[3] |
1761 |
1 |
|
T1 |
20 |
|
T2 |
1 |
|
T4 |
14 |
| false |
552 |
1 |
|
T1 |
3 |
|
T4 |
9 |
|
T53 |
3 |
| true |
1383 |
1 |
|
T4 |
54 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T20 |
1 |
|
T21 |
2 |
|
T63 |
1 |
| others[1] |
242 |
1 |
|
T21 |
1 |
|
T391 |
1 |
|
T95 |
1 |
| others[2] |
271 |
1 |
|
T405 |
1 |
|
T401 |
1 |
|
T246 |
1 |
| others[3] |
367 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| false |
138 |
1 |
|
T400 |
1 |
|
T205 |
1 |
|
T103 |
8 |
| true |
5606 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T183 |
1 |
|
T273 |
1 |
|
T70 |
1 |
| others[1] |
221 |
1 |
|
T35 |
1 |
|
T26 |
1 |
|
T400 |
1 |
| others[2] |
228 |
1 |
|
T18 |
1 |
|
T391 |
1 |
|
T246 |
1 |
| others[3] |
361 |
1 |
|
T21 |
1 |
|
T159 |
1 |
|
T391 |
1 |
| false |
128 |
1 |
|
T403 |
1 |
|
T103 |
7 |
|
T396 |
1 |
| true |
5704 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T1 |
11 |
|
T4 |
13 |
|
T53 |
23 |
| others[1] |
1218 |
1 |
|
T1 |
5 |
|
T4 |
22 |
|
T53 |
13 |
| others[2] |
1175 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
23 |
| others[3] |
2165 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T4 |
34 |
| false |
634 |
1 |
|
T1 |
10 |
|
T4 |
8 |
|
T22 |
1 |
| true |
448 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T1 |
7 |
|
T4 |
17 |
|
T20 |
1 |
| others[1] |
1232 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T4 |
21 |
| others[2] |
1216 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
12 |
| others[3] |
2066 |
1 |
|
T1 |
18 |
|
T4 |
39 |
|
T8 |
1 |
| false |
656 |
1 |
|
T1 |
5 |
|
T4 |
11 |
|
T58 |
1 |
| true |
426 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T2 |
1 |
|
T21 |
3 |
|
T35 |
1 |
| others[1] |
113 |
1 |
|
T393 |
1 |
|
T183 |
1 |
|
T26 |
1 |
| others[2] |
101 |
1 |
|
T33 |
1 |
|
T391 |
1 |
|
T70 |
1 |
| others[3] |
170 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T393 |
1 |
| false |
54 |
1 |
|
T391 |
1 |
|
T246 |
1 |
|
T103 |
3 |
| true |
6325 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T21 |
1 |
|
T24 |
1 |
|
T31 |
1 |
| others[1] |
242 |
1 |
|
T21 |
1 |
|
T159 |
1 |
|
T44 |
1 |
| others[2] |
238 |
1 |
|
T278 |
1 |
|
T393 |
1 |
|
T266 |
1 |
| others[3] |
409 |
1 |
|
T2 |
1 |
|
T32 |
1 |
|
T237 |
1 |
| false |
115 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T21 |
1 |
| true |
5629 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1087 |
1 |
|
T1 |
4 |
|
T4 |
12 |
|
T5 |
1 |
| others[1] |
1040 |
1 |
|
T1 |
9 |
|
T4 |
16 |
|
T22 |
1 |
| others[2] |
1010 |
1 |
|
T1 |
16 |
|
T2 |
1 |
|
T4 |
9 |
| others[3] |
1764 |
1 |
|
T1 |
14 |
|
T4 |
9 |
|
T8 |
1 |
| false |
544 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T4 |
3 |
| true |
1412 |
1 |
|
T4 |
51 |
|
T18 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T48 |
1 |
|
T31 |
1 |
|
T188 |
1 |
| others[1] |
259 |
1 |
|
T21 |
1 |
|
T23 |
1 |
|
T391 |
1 |
| others[2] |
207 |
1 |
|
T159 |
1 |
|
T57 |
1 |
|
T103 |
7 |
| others[3] |
377 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T21 |
1 |
| false |
97 |
1 |
|
T56 |
1 |
|
T246 |
1 |
|
T103 |
4 |
| true |
5697 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
100 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T159 |
1 |
| others[1] |
216 |
1 |
|
T21 |
1 |
|
T34 |
1 |
|
T26 |
1 |
| others[2] |
198 |
1 |
|
T400 |
1 |
|
T103 |
7 |
|
T104 |
9 |
| others[3] |
377 |
1 |
|
T2 |
1 |
|
T311 |
1 |
|
T95 |
1 |
| false |
128 |
1 |
|
T56 |
1 |
|
T246 |
1 |
|
T103 |
3 |
| true |
5708 |
1 |
|
T1 |
47 |
|
T4 |
100 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T1 |
7 |
|
T4 |
14 |
|
T21 |
1 |
| others[1] |
1283 |
1 |
|
T1 |
8 |
|
T2 |
2 |
|
T4 |
21 |
| others[2] |
1252 |
1 |
|
T1 |
9 |
|
T4 |
17 |
|
T8 |
1 |
| others[3] |
2075 |
1 |
|
T1 |
17 |
|
T4 |
40 |
|
T5 |
1 |
| false |
579 |
1 |
|
T1 |
6 |
|
T4 |
8 |
|
T53 |
6 |
| true |
445 |
1 |
|
T6 |
1 |
|
T12 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T52 |
1 |
|
T144 |
1 |
|
T406 |
1 |
| others[1] |
11 |
1 |
|
T12 |
1 |
|
T138 |
2 |
|
T407 |
1 |
| others[2] |
7 |
1 |
|
T115 |
1 |
|
T141 |
1 |
|
T408 |
1 |
| others[3] |
12 |
1 |
|
T73 |
1 |
|
T74 |
1 |
|
T129 |
2 |
| false |
2 |
1 |
|
T409 |
1 |
|
T410 |
1 |
|
- |
- |
| true |
36 |
1 |
|
T3 |
1 |
|
T52 |
1 |
|
T68 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T27 |
1 |
|
T389 |
1 |
|
T411 |
1 |
| others[1] |
3 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T412 |
1 |
| others[2] |
1 |
1 |
|
T413 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
4 |
1 |
|
T414 |
1 |
|
T415 |
1 |
|
T416 |
1 |
| false |
10 |
1 |
|
T91 |
1 |
|
T384 |
1 |
|
T182 |
1 |
| true |
25 |
1 |
|
T236 |
1 |
|
T186 |
1 |
|
T417 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |