Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10395 |
1 |
|
T1 |
11 |
|
T4 |
100 |
|
T21 |
4 |
| others[1] |
746 |
1 |
|
T1 |
7 |
|
T41 |
1 |
|
T54 |
8 |
| others[2] |
820 |
1 |
|
T1 |
12 |
|
T8 |
1 |
|
T21 |
1 |
| others[3] |
1312 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T22 |
1 |
| false |
402 |
1 |
|
T1 |
7 |
|
T49 |
1 |
|
T54 |
5 |
| true |
528 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2382 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
21 |
| others[1] |
2424 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T4 |
21 |
| others[2] |
2404 |
1 |
|
T1 |
7 |
|
T4 |
12 |
|
T22 |
1 |
| others[3] |
4099 |
1 |
|
T1 |
21 |
|
T4 |
32 |
|
T21 |
2 |
| false |
1299 |
1 |
|
T1 |
1 |
|
T4 |
14 |
|
T8 |
1 |
| true |
1595 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9831 |
1 |
|
T4 |
100 |
|
T5 |
1 |
|
T59 |
1 |
| others[1] |
279 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T22 |
1 |
| others[2] |
284 |
1 |
|
T18 |
1 |
|
T31 |
1 |
|
T278 |
1 |
| others[3] |
447 |
1 |
|
T33 |
1 |
|
T58 |
1 |
|
T41 |
4 |
| false |
136 |
1 |
|
T44 |
1 |
|
T71 |
1 |
|
T103 |
3 |
| true |
3226 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10056 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T4 |
100 |
| others[1] |
497 |
1 |
|
T1 |
4 |
|
T7 |
1 |
|
T24 |
1 |
| others[2] |
446 |
1 |
|
T1 |
4 |
|
T8 |
1 |
|
T21 |
1 |
| others[3] |
754 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T6 |
1 |
| false |
231 |
1 |
|
T1 |
4 |
|
T21 |
2 |
|
T32 |
1 |
| true |
2219 |
1 |
|
T1 |
24 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9826 |
1 |
|
T4 |
100 |
|
T21 |
2 |
|
T58 |
1 |
| others[1] |
258 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| others[2] |
246 |
1 |
|
T22 |
1 |
|
T391 |
1 |
|
T335 |
1 |
| others[3] |
433 |
1 |
|
T20 |
1 |
|
T25 |
1 |
|
T159 |
1 |
| false |
139 |
1 |
|
T18 |
1 |
|
T64 |
1 |
|
T41 |
1 |
| true |
3301 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9812 |
1 |
|
T4 |
100 |
|
T22 |
1 |
|
T21 |
1 |
| others[1] |
270 |
1 |
|
T21 |
2 |
|
T41 |
2 |
|
T50 |
1 |
| others[2] |
250 |
1 |
|
T44 |
1 |
|
T94 |
1 |
|
T103 |
8 |
| others[3] |
417 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| false |
141 |
1 |
|
T2 |
1 |
|
T222 |
1 |
|
T397 |
1 |
| true |
3313 |
1 |
|
T1 |
47 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10394 |
1 |
|
T1 |
13 |
|
T2 |
1 |
|
T4 |
100 |
| others[1] |
792 |
1 |
|
T1 |
10 |
|
T24 |
1 |
|
T151 |
1 |
| others[2] |
836 |
1 |
|
T1 |
7 |
|
T21 |
1 |
|
T50 |
1 |
| others[3] |
1283 |
1 |
|
T1 |
14 |
|
T21 |
1 |
|
T58 |
1 |
| false |
394 |
1 |
|
T1 |
3 |
|
T22 |
1 |
|
T63 |
1 |
| true |
504 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10358 |
1 |
|
T1 |
9 |
|
T4 |
100 |
|
T21 |
1 |
| others[1] |
795 |
1 |
|
T1 |
5 |
|
T50 |
1 |
|
T54 |
12 |
| others[2] |
755 |
1 |
|
T1 |
11 |
|
T21 |
1 |
|
T58 |
1 |
| others[3] |
1306 |
1 |
|
T1 |
18 |
|
T22 |
1 |
|
T8 |
1 |
| false |
416 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T151 |
1 |
| true |
534 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2410 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
10 |
| others[1] |
2449 |
1 |
|
T1 |
10 |
|
T4 |
24 |
|
T8 |
1 |
| others[2] |
2460 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
18 |
| others[3] |
4023 |
1 |
|
T1 |
21 |
|
T4 |
33 |
|
T22 |
1 |
| false |
1256 |
1 |
|
T1 |
4 |
|
T4 |
15 |
|
T77 |
16 |
| true |
1566 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9818 |
1 |
|
T2 |
1 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
286 |
1 |
|
T23 |
1 |
|
T151 |
1 |
|
T101 |
1 |
| others[2] |
233 |
1 |
|
T41 |
1 |
|
T32 |
1 |
|
T49 |
1 |
| others[3] |
454 |
1 |
|
T21 |
1 |
|
T41 |
1 |
|
T34 |
1 |
| false |
146 |
1 |
|
T21 |
1 |
|
T44 |
1 |
|
T92 |
1 |
| true |
3227 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10028 |
1 |
|
T1 |
5 |
|
T4 |
100 |
|
T8 |
1 |
| others[1] |
470 |
1 |
|
T1 |
4 |
|
T2 |
2 |
|
T31 |
1 |
| others[2] |
472 |
1 |
|
T1 |
6 |
|
T21 |
2 |
|
T51 |
1 |
| others[3] |
743 |
1 |
|
T1 |
9 |
|
T21 |
1 |
|
T65 |
1 |
| false |
243 |
1 |
|
T21 |
1 |
|
T25 |
1 |
|
T41 |
1 |
| true |
2208 |
1 |
|
T1 |
23 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9814 |
1 |
|
T2 |
1 |
|
T4 |
100 |
|
T21 |
1 |
| others[1] |
255 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T48 |
1 |
| others[2] |
237 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T170 |
1 |
| others[3] |
417 |
1 |
|
T22 |
1 |
|
T33 |
1 |
|
T41 |
1 |
| false |
154 |
1 |
|
T8 |
1 |
|
T23 |
1 |
|
T44 |
1 |
| true |
3287 |
1 |
|
T1 |
47 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9810 |
1 |
|
T4 |
100 |
|
T59 |
1 |
|
T77 |
193 |
| others[1] |
236 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T58 |
1 |
| others[2] |
265 |
1 |
|
T18 |
1 |
|
T25 |
1 |
|
T41 |
1 |
| others[3] |
447 |
1 |
|
T34 |
1 |
|
T92 |
1 |
|
T56 |
1 |
| false |
132 |
1 |
|
T21 |
1 |
|
T41 |
1 |
|
T28 |
1 |
| true |
3274 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10378 |
1 |
|
T1 |
8 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
801 |
1 |
|
T1 |
11 |
|
T22 |
1 |
|
T54 |
15 |
| others[2] |
761 |
1 |
|
T1 |
5 |
|
T21 |
2 |
|
T41 |
1 |
| others[3] |
1301 |
1 |
|
T1 |
17 |
|
T8 |
1 |
|
T58 |
1 |
| false |
412 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T28 |
1 |
| true |
511 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10333 |
1 |
|
T1 |
8 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
780 |
1 |
|
T1 |
11 |
|
T8 |
1 |
|
T151 |
1 |
| others[2] |
800 |
1 |
|
T1 |
13 |
|
T18 |
1 |
|
T21 |
1 |
| others[3] |
1347 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T22 |
1 |
| false |
391 |
1 |
|
T1 |
4 |
|
T54 |
11 |
|
T69 |
2 |
| true |
513 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2423 |
1 |
|
T1 |
13 |
|
T4 |
16 |
|
T59 |
1 |
| others[1] |
2416 |
1 |
|
T1 |
5 |
|
T4 |
20 |
|
T18 |
1 |
| others[2] |
2409 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
15 |
| others[3] |
4058 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T4 |
40 |
| false |
1276 |
1 |
|
T4 |
9 |
|
T33 |
1 |
|
T77 |
25 |
| true |
1582 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9830 |
1 |
|
T4 |
100 |
|
T59 |
1 |
|
T77 |
193 |
| others[1] |
260 |
1 |
|
T41 |
1 |
|
T35 |
1 |
|
T393 |
2 |
| others[2] |
268 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T28 |
1 |
| others[3] |
425 |
1 |
|
T33 |
1 |
|
T23 |
1 |
|
T48 |
1 |
| false |
147 |
1 |
|
T25 |
1 |
|
T41 |
1 |
|
T93 |
1 |
| true |
3234 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10033 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
100 |
| others[1] |
488 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T5 |
1 |
| others[2] |
465 |
1 |
|
T8 |
1 |
|
T21 |
2 |
|
T13 |
1 |
| others[3] |
782 |
1 |
|
T1 |
8 |
|
T22 |
1 |
|
T21 |
1 |
| false |
236 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T41 |
1 |
| true |
2160 |
1 |
|
T1 |
29 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9810 |
1 |
|
T4 |
100 |
|
T21 |
1 |
|
T59 |
1 |
| others[1] |
253 |
1 |
|
T2 |
1 |
|
T48 |
1 |
|
T41 |
1 |
| others[2] |
264 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T58 |
1 |
| others[3] |
426 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T159 |
1 |
| false |
141 |
1 |
|
T22 |
1 |
|
T21 |
2 |
|
T170 |
1 |
| true |
3270 |
1 |
|
T1 |
47 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9779 |
1 |
|
T2 |
1 |
|
T4 |
100 |
|
T21 |
1 |
| others[1] |
261 |
1 |
|
T41 |
1 |
|
T188 |
1 |
|
T397 |
1 |
| others[2] |
266 |
1 |
|
T64 |
1 |
|
T41 |
1 |
|
T43 |
1 |
| others[3] |
410 |
1 |
|
T18 |
1 |
|
T8 |
1 |
|
T21 |
2 |
| false |
125 |
1 |
|
T44 |
1 |
|
T56 |
1 |
|
T100 |
1 |
| true |
3323 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10341 |
1 |
|
T1 |
6 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
801 |
1 |
|
T1 |
10 |
|
T22 |
1 |
|
T41 |
3 |
| others[2] |
789 |
1 |
|
T1 |
9 |
|
T25 |
1 |
|
T50 |
1 |
| others[3] |
1364 |
1 |
|
T1 |
16 |
|
T21 |
1 |
|
T58 |
1 |
| false |
389 |
1 |
|
T1 |
6 |
|
T8 |
1 |
|
T41 |
1 |
| true |
480 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10357 |
1 |
|
T1 |
11 |
|
T4 |
100 |
|
T8 |
1 |
| others[1] |
766 |
1 |
|
T1 |
8 |
|
T49 |
1 |
|
T151 |
1 |
| others[2] |
793 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T18 |
1 |
| others[3] |
1326 |
1 |
|
T1 |
14 |
|
T22 |
1 |
|
T58 |
1 |
| false |
397 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T54 |
3 |
| true |
525 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2427 |
1 |
|
T1 |
12 |
|
T4 |
24 |
|
T22 |
1 |
| others[1] |
2371 |
1 |
|
T1 |
10 |
|
T4 |
27 |
|
T21 |
1 |
| others[2] |
2446 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
16 |
| others[3] |
4079 |
1 |
|
T1 |
13 |
|
T4 |
27 |
|
T8 |
1 |
| false |
1261 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T4 |
6 |
| true |
1580 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9802 |
1 |
|
T4 |
100 |
|
T21 |
1 |
|
T59 |
1 |
| others[1] |
274 |
1 |
|
T2 |
1 |
|
T41 |
1 |
|
T63 |
1 |
| others[2] |
286 |
1 |
|
T33 |
1 |
|
T48 |
1 |
|
T41 |
2 |
| others[3] |
475 |
1 |
|
T21 |
1 |
|
T64 |
1 |
|
T23 |
1 |
| false |
132 |
1 |
|
T41 |
1 |
|
T32 |
1 |
|
T100 |
1 |
| true |
3195 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10032 |
1 |
|
T1 |
4 |
|
T4 |
100 |
|
T12 |
1 |
| others[1] |
428 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T41 |
1 |
| others[2] |
478 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T21 |
3 |
| others[3] |
813 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T7 |
1 |
| false |
220 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T58 |
1 |
| true |
2193 |
1 |
|
T1 |
25 |
|
T18 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9841 |
1 |
|
T4 |
100 |
|
T21 |
1 |
|
T59 |
1 |
| others[1] |
278 |
1 |
|
T5 |
1 |
|
T159 |
1 |
|
T237 |
1 |
| others[2] |
267 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T58 |
1 |
| others[3] |
425 |
1 |
|
T18 |
1 |
|
T31 |
1 |
|
T63 |
1 |
| false |
150 |
1 |
|
T100 |
1 |
|
T103 |
8 |
|
T418 |
1 |
| true |
3203 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9819 |
1 |
|
T4 |
100 |
|
T59 |
1 |
|
T77 |
193 |
| others[1] |
246 |
1 |
|
T21 |
2 |
|
T25 |
1 |
|
T56 |
1 |
| others[2] |
252 |
1 |
|
T22 |
1 |
|
T58 |
1 |
|
T41 |
1 |
| others[3] |
393 |
1 |
|
T2 |
2 |
|
T41 |
1 |
|
T34 |
1 |
| false |
109 |
1 |
|
T33 |
1 |
|
T391 |
1 |
|
T307 |
1 |
| true |
3345 |
1 |
|
T1 |
47 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10361 |
1 |
|
T1 |
12 |
|
T4 |
100 |
|
T21 |
1 |
| others[1] |
784 |
1 |
|
T1 |
7 |
|
T2 |
2 |
|
T22 |
1 |
| others[2] |
803 |
1 |
|
T1 |
13 |
|
T8 |
1 |
|
T25 |
1 |
| others[3] |
1304 |
1 |
|
T1 |
12 |
|
T21 |
3 |
|
T58 |
1 |
| false |
407 |
1 |
|
T1 |
3 |
|
T54 |
3 |
|
T170 |
1 |
| true |
505 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10342 |
1 |
|
T1 |
15 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
760 |
1 |
|
T1 |
7 |
|
T32 |
1 |
|
T28 |
1 |
| others[2] |
795 |
1 |
|
T1 |
7 |
|
T8 |
1 |
|
T25 |
1 |
| others[3] |
1324 |
1 |
|
T1 |
17 |
|
T151 |
1 |
|
T54 |
18 |
| false |
404 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T22 |
1 |
| true |
539 |
1 |
|
T2 |
2 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2560 |
1 |
|
T1 |
7 |
|
T4 |
18 |
|
T58 |
1 |
| others[1] |
2385 |
1 |
|
T1 |
6 |
|
T4 |
26 |
|
T21 |
1 |
| others[2] |
2369 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
15 |
| others[3] |
4065 |
1 |
|
T1 |
19 |
|
T4 |
36 |
|
T22 |
1 |
| false |
1246 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T4 |
5 |
| true |
1539 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9815 |
1 |
|
T4 |
100 |
|
T20 |
1 |
|
T59 |
1 |
| others[1] |
270 |
1 |
|
T5 |
1 |
|
T22 |
1 |
|
T48 |
1 |
| others[2] |
290 |
1 |
|
T21 |
1 |
|
T100 |
1 |
|
T311 |
1 |
| others[3] |
442 |
1 |
|
T64 |
1 |
|
T23 |
1 |
|
T31 |
1 |
| false |
117 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T237 |
1 |
| true |
3230 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |