Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10028 |
1 |
|
T1 |
6 |
|
T2 |
2 |
|
T4 |
100 |
| others[1] |
439 |
1 |
|
T1 |
5 |
|
T34 |
1 |
|
T54 |
6 |
| others[2] |
460 |
1 |
|
T1 |
5 |
|
T5 |
1 |
|
T8 |
1 |
| others[3] |
777 |
1 |
|
T1 |
4 |
|
T21 |
3 |
|
T51 |
1 |
| false |
249 |
1 |
|
T1 |
2 |
|
T6 |
1 |
|
T7 |
1 |
| true |
2211 |
1 |
|
T1 |
25 |
|
T12 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9814 |
1 |
|
T4 |
100 |
|
T8 |
1 |
|
T59 |
1 |
| others[1] |
257 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T92 |
1 |
| others[2] |
288 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T21 |
2 |
| others[3] |
386 |
1 |
|
T18 |
1 |
|
T22 |
1 |
|
T58 |
1 |
| false |
137 |
1 |
|
T31 |
1 |
|
T93 |
1 |
|
T393 |
1 |
| true |
3282 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9810 |
1 |
|
T4 |
100 |
|
T59 |
1 |
|
T77 |
193 |
| others[1] |
274 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T159 |
1 |
| others[2] |
236 |
1 |
|
T8 |
1 |
|
T21 |
1 |
|
T25 |
1 |
| others[3] |
394 |
1 |
|
T2 |
2 |
|
T58 |
1 |
|
T41 |
1 |
| false |
139 |
1 |
|
T64 |
1 |
|
T215 |
1 |
|
T222 |
1 |
| true |
3311 |
1 |
|
T1 |
47 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10370 |
1 |
|
T1 |
11 |
|
T4 |
100 |
|
T58 |
1 |
| others[1] |
793 |
1 |
|
T1 |
9 |
|
T54 |
12 |
|
T69 |
4 |
| others[2] |
808 |
1 |
|
T1 |
13 |
|
T20 |
1 |
|
T22 |
1 |
| others[3] |
1296 |
1 |
|
T1 |
12 |
|
T8 |
1 |
|
T21 |
1 |
| false |
394 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T54 |
5 |
| true |
503 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10320 |
1 |
|
T1 |
9 |
|
T4 |
100 |
|
T8 |
1 |
| others[1] |
762 |
1 |
|
T1 |
10 |
|
T22 |
1 |
|
T58 |
1 |
| others[2] |
791 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T41 |
1 |
| others[3] |
1340 |
1 |
|
T1 |
15 |
|
T21 |
1 |
|
T65 |
1 |
| false |
447 |
1 |
|
T1 |
6 |
|
T31 |
1 |
|
T50 |
1 |
| true |
504 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2395 |
1 |
|
T1 |
13 |
|
T2 |
1 |
|
T4 |
12 |
| others[1] |
2456 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
23 |
| others[2] |
2370 |
1 |
|
T1 |
5 |
|
T4 |
14 |
|
T21 |
1 |
| others[3] |
4128 |
1 |
|
T1 |
18 |
|
T4 |
42 |
|
T22 |
1 |
| false |
1228 |
1 |
|
T1 |
3 |
|
T4 |
9 |
|
T77 |
19 |
| true |
1587 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9805 |
1 |
|
T4 |
100 |
|
T20 |
1 |
|
T59 |
1 |
| others[1] |
257 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T64 |
1 |
| others[2] |
282 |
1 |
|
T5 |
1 |
|
T22 |
1 |
|
T21 |
1 |
| others[3] |
433 |
1 |
|
T21 |
1 |
|
T43 |
1 |
|
T50 |
1 |
| false |
170 |
1 |
|
T21 |
1 |
|
T58 |
1 |
|
T63 |
1 |
| true |
3217 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9993 |
1 |
|
T1 |
4 |
|
T4 |
100 |
|
T18 |
1 |
| others[1] |
457 |
1 |
|
T1 |
4 |
|
T12 |
1 |
|
T7 |
1 |
| others[2] |
506 |
1 |
|
T1 |
6 |
|
T2 |
2 |
|
T20 |
1 |
| others[3] |
775 |
1 |
|
T1 |
6 |
|
T6 |
1 |
|
T21 |
1 |
| false |
232 |
1 |
|
T1 |
5 |
|
T41 |
1 |
|
T151 |
1 |
| true |
2201 |
1 |
|
T1 |
22 |
|
T5 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9801 |
1 |
|
T4 |
100 |
|
T59 |
1 |
|
T77 |
193 |
| others[1] |
266 |
1 |
|
T25 |
1 |
|
T93 |
1 |
|
T237 |
1 |
| others[2] |
236 |
1 |
|
T33 |
1 |
|
T159 |
1 |
|
T34 |
1 |
| others[3] |
425 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T56 |
1 |
| false |
148 |
1 |
|
T21 |
1 |
|
T41 |
1 |
|
T57 |
1 |
| true |
3288 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9815 |
1 |
|
T4 |
100 |
|
T21 |
1 |
|
T59 |
1 |
| others[1] |
233 |
1 |
|
T21 |
1 |
|
T41 |
1 |
|
T311 |
1 |
| others[2] |
242 |
1 |
|
T21 |
1 |
|
T25 |
1 |
|
T57 |
1 |
| others[3] |
447 |
1 |
|
T21 |
1 |
|
T58 |
1 |
|
T41 |
1 |
| false |
128 |
1 |
|
T151 |
1 |
|
T183 |
1 |
|
T394 |
1 |
| true |
3299 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10325 |
1 |
|
T1 |
9 |
|
T4 |
100 |
|
T8 |
1 |
| others[1] |
818 |
1 |
|
T1 |
8 |
|
T22 |
1 |
|
T41 |
2 |
| others[2] |
743 |
1 |
|
T1 |
6 |
|
T21 |
1 |
|
T28 |
1 |
| others[3] |
1332 |
1 |
|
T1 |
15 |
|
T21 |
1 |
|
T58 |
1 |
| false |
433 |
1 |
|
T1 |
9 |
|
T54 |
4 |
|
T170 |
1 |
| true |
513 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10348 |
1 |
|
T1 |
6 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
768 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T20 |
1 |
| others[2] |
762 |
1 |
|
T1 |
12 |
|
T21 |
1 |
|
T41 |
1 |
| others[3] |
1307 |
1 |
|
T1 |
15 |
|
T31 |
1 |
|
T41 |
1 |
| false |
447 |
1 |
|
T1 |
5 |
|
T8 |
1 |
|
T58 |
1 |
| true |
532 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2419 |
1 |
|
T1 |
8 |
|
T4 |
19 |
|
T59 |
1 |
| others[1] |
2460 |
1 |
|
T1 |
7 |
|
T4 |
21 |
|
T21 |
1 |
| others[2] |
2376 |
1 |
|
T1 |
12 |
|
T4 |
17 |
|
T21 |
1 |
| others[3] |
4058 |
1 |
|
T1 |
13 |
|
T2 |
1 |
|
T4 |
31 |
| false |
1265 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
12 |
| true |
1586 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9819 |
1 |
|
T4 |
100 |
|
T59 |
1 |
|
T77 |
193 |
| others[1] |
268 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T41 |
1 |
| others[2] |
287 |
1 |
|
T21 |
1 |
|
T33 |
1 |
|
T100 |
1 |
| others[3] |
448 |
1 |
|
T21 |
2 |
|
T58 |
1 |
|
T23 |
1 |
| false |
127 |
1 |
|
T181 |
1 |
|
T351 |
1 |
|
T394 |
1 |
| true |
3215 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10047 |
1 |
|
T1 |
1 |
|
T4 |
100 |
|
T21 |
1 |
| others[1] |
450 |
1 |
|
T1 |
6 |
|
T21 |
2 |
|
T159 |
1 |
| others[2] |
453 |
1 |
|
T1 |
3 |
|
T2 |
1 |
|
T21 |
1 |
| others[3] |
789 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T5 |
1 |
| false |
205 |
1 |
|
T1 |
2 |
|
T12 |
1 |
|
T65 |
1 |
| true |
2220 |
1 |
|
T1 |
25 |
|
T6 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9799 |
1 |
|
T4 |
100 |
|
T5 |
1 |
|
T33 |
1 |
| others[1] |
280 |
1 |
|
T21 |
1 |
|
T41 |
2 |
|
T34 |
1 |
| others[2] |
266 |
1 |
|
T32 |
1 |
|
T100 |
1 |
|
T339 |
1 |
| others[3] |
440 |
1 |
|
T21 |
2 |
|
T170 |
1 |
|
T35 |
1 |
| false |
148 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T395 |
1 |
| true |
3231 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9798 |
1 |
|
T4 |
100 |
|
T21 |
1 |
|
T58 |
1 |
| others[1] |
224 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T41 |
1 |
| others[2] |
247 |
1 |
|
T18 |
1 |
|
T183 |
1 |
|
T94 |
1 |
| others[3] |
440 |
1 |
|
T21 |
1 |
|
T64 |
1 |
|
T41 |
1 |
| false |
135 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T57 |
1 |
| true |
3320 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10369 |
1 |
|
T1 |
11 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
764 |
1 |
|
T1 |
6 |
|
T22 |
1 |
|
T21 |
1 |
| others[2] |
784 |
1 |
|
T1 |
11 |
|
T25 |
1 |
|
T54 |
11 |
| others[3] |
1358 |
1 |
|
T1 |
17 |
|
T21 |
1 |
|
T58 |
1 |
| false |
404 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T8 |
1 |
| true |
485 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10366 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T4 |
100 |
| others[1] |
783 |
1 |
|
T1 |
11 |
|
T50 |
1 |
|
T54 |
10 |
| others[2] |
791 |
1 |
|
T1 |
8 |
|
T22 |
1 |
|
T21 |
1 |
| others[3] |
1312 |
1 |
|
T1 |
13 |
|
T64 |
1 |
|
T65 |
1 |
| false |
390 |
1 |
|
T1 |
4 |
|
T41 |
1 |
|
T49 |
1 |
| true |
522 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2447 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
22 |
| others[1] |
2365 |
1 |
|
T1 |
10 |
|
T4 |
16 |
|
T18 |
1 |
| others[2] |
2477 |
1 |
|
T1 |
11 |
|
T4 |
23 |
|
T8 |
1 |
| others[3] |
4070 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T4 |
32 |
| false |
1241 |
1 |
|
T1 |
4 |
|
T4 |
7 |
|
T22 |
1 |
| true |
1564 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9828 |
1 |
|
T4 |
100 |
|
T5 |
1 |
|
T59 |
1 |
| others[1] |
250 |
1 |
|
T24 |
1 |
|
T48 |
1 |
|
T57 |
1 |
| others[2] |
259 |
1 |
|
T18 |
1 |
|
T28 |
1 |
|
T278 |
1 |
| others[3] |
495 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T21 |
2 |
| false |
156 |
1 |
|
T41 |
1 |
|
T36 |
1 |
|
T237 |
1 |
| true |
3176 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9992 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T4 |
100 |
| others[1] |
469 |
1 |
|
T1 |
2 |
|
T6 |
1 |
|
T21 |
2 |
| others[2] |
481 |
1 |
|
T1 |
4 |
|
T21 |
1 |
|
T23 |
1 |
| others[3] |
774 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T12 |
1 |
| false |
245 |
1 |
|
T1 |
2 |
|
T41 |
2 |
|
T278 |
1 |
| true |
2203 |
1 |
|
T1 |
26 |
|
T5 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9816 |
1 |
|
T4 |
100 |
|
T5 |
1 |
|
T58 |
1 |
| others[1] |
269 |
1 |
|
T48 |
1 |
|
T41 |
1 |
|
T34 |
1 |
| others[2] |
294 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T41 |
1 |
| others[3] |
419 |
1 |
|
T20 |
1 |
|
T22 |
1 |
|
T21 |
1 |
| false |
133 |
1 |
|
T391 |
1 |
|
T246 |
1 |
|
T103 |
8 |
| true |
3233 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9833 |
1 |
|
T4 |
100 |
|
T64 |
1 |
|
T59 |
1 |
| others[1] |
219 |
1 |
|
T44 |
1 |
|
T95 |
1 |
|
T273 |
1 |
| others[2] |
254 |
1 |
|
T22 |
1 |
|
T33 |
1 |
|
T41 |
2 |
| others[3] |
424 |
1 |
|
T21 |
2 |
|
T58 |
1 |
|
T41 |
1 |
| false |
126 |
1 |
|
T18 |
1 |
|
T151 |
1 |
|
T307 |
1 |
| true |
3308 |
1 |
|
T1 |
47 |
|
T2 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10343 |
1 |
|
T1 |
7 |
|
T4 |
100 |
|
T59 |
1 |
| others[1] |
788 |
1 |
|
T1 |
12 |
|
T2 |
2 |
|
T58 |
1 |
| others[2] |
802 |
1 |
|
T1 |
8 |
|
T21 |
2 |
|
T54 |
16 |
| others[3] |
1309 |
1 |
|
T1 |
16 |
|
T18 |
1 |
|
T22 |
1 |
| false |
417 |
1 |
|
T1 |
4 |
|
T49 |
1 |
|
T54 |
5 |
| true |
505 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T12 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |