Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	228741	1		T1	37		T2	4		T4	600
auto[FlashEraseBank]	254079	1		T1	10		T2	1		T5	30

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	265611	1		T1	47		T2	3		T4	200
auto[FlashOpProgram]	197432	1		T4	100		T5	34		T17	128
auto[FlashOpErase]	15777	1		T2	2		T4	100		T12	1
auto[FlashOpInvalid]	4000	1		T4	200		T53	200		T98	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	265611	1		T1	47		T2	3		T4	200
op[FlashOpProgram]	197432	1		T4	100		T5	34		T17	128
op[FlashOpErase]	15777	1		T2	2		T4	100		T12	1
read_erase_read	725	1		T2	1		T17	1		T19	1
read_prog_read	1377	1		T5	24		T8	1		T33	7

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	340946	1		T1	47		T2	5		T4	594
auto[FlashPartInfo]	137821	1		T4	6		T5	57		T17	154
auto[FlashPartInfo1]	922	1		T8	3		T33	3		T58	2
auto[FlashPartInfo2]	3131	1		T5	1		T20	2		T8	13

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	200358	1		T1	47		T2	3		T4	198
auto[FlashPartData]	auto[FlashOpProgram]	132966	1		T4	99		T5	9		T22	893
auto[FlashPartData]	auto[FlashOpErase]	3718	1		T2	2		T4	99		T12	1
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T4	198		T53	198		T98	190
auto[FlashPartInfo]	auto[FlashOpRead]	62496	1		T4	2		T5	32		T17	14
auto[FlashPartInfo]	auto[FlashOpProgram]	63254	1		T4	1		T5	25		T17	128
auto[FlashPartInfo]	auto[FlashOpErase]	11991	1		T4	1		T17	12		T19	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T4	2		T53	2		T98	10
auto[FlashPartInfo1]	auto[FlashOpRead]	742	1		T8	3		T33	3		T58	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	167	1		T59	32		T80	1		T104	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T80	1		T85	1		T419	2
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T80	2		T419	4		T420	2
auto[FlashPartInfo2]	auto[FlashOpRead]	2015	1		T5	1		T20	2		T8	10
auto[FlashPartInfo2]	auto[FlashOpProgram]	1045	1		T8	3		T33	15		T64	1
auto[FlashPartInfo2]	auto[FlashOpErase]	63	1		T94	1		T140	1		T421	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T421	2		T110	2		T422	2