Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30520	1		T2	3		T4	400		T19	4
auto[1]	22	1		T20	1		T24	3		T37	1
auto[2]	99	1		T5	2		T37	1		T346	2
auto[3]	363	1		T63	6		T36	1		T279	3

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7783	1		T2	1		T4	100		T19	1
evic_idx[1]	7763	1		T2	1		T4	100		T19	1
evic_idx[2]	7729	1		T2	1		T4	100		T5	1
evic_idx[3]	7729	1		T4	100		T5	1		T19	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29879	1		T4	400		T20	1		T77	592
evic_op[2]	527	1		T5	2		T19	4		T24	3

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1] , evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[1]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7384	1		T4	100		T77	148		T53	100
evic_idx[0]	evic_op[1]	auto[1]	1	1		T20	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	8	1		T347	4		T348	4		-	-
evic_idx[0]	evic_op[1]	auto[3]	111	1		T63	2		T349	38		T350	4
evic_idx[0]	evic_op[2]	auto[0]	94	1		T19	1		T351	4		T205	1
evic_idx[0]	evic_op[2]	auto[1]	6	1		T24	1		T37	1		T352	1
evic_idx[0]	evic_op[2]	auto[2]	16	1		T353	9		T354	1		T355	6
evic_idx[0]	evic_op[2]	auto[3]	13	1		T36	1		T356	1		T357	1
evic_idx[1]	evic_op[1]	auto[0]	7385	1		T4	100		T77	148		T53	100
evic_idx[1]	evic_op[1]	auto[2]	4	1		T347	3		T348	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	80	1		T63	2		T349	23		T358	5
evic_idx[1]	evic_op[2]	auto[0]	108	1		T19	1		T189	1		T351	4
evic_idx[1]	evic_op[2]	auto[1]	3	1		T166	1		T359	1		T360	1
evic_idx[1]	evic_op[2]	auto[2]	19	1		T37	1		T346	2		T353	6
evic_idx[1]	evic_op[2]	auto[3]	14	1		T279	1		T356	1		T361	1
evic_idx[2]	evic_op[1]	auto[0]	7390	1		T4	100		T77	148		T53	100
evic_idx[2]	evic_op[1]	auto[2]	4	1		T347	3		T348	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	60	1		T63	1		T349	14		T350	1
evic_idx[2]	evic_op[2]	auto[0]	97	1		T19	1		T101	2		T351	4
evic_idx[2]	evic_op[2]	auto[1]	5	1		T24	1		T166	1		T362	1
evic_idx[2]	evic_op[2]	auto[2]	13	1		T5	1		T353	5		T355	7
evic_idx[2]	evic_op[2]	auto[3]	10	1		T279	1		T356	1		T361	1
evic_idx[3]	evic_op[1]	auto[0]	7386	1		T4	100		T77	148		T53	100
evic_idx[3]	evic_op[1]	auto[2]	6	1		T347	5		T348	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	60	1		T63	1		T349	9		T350	2
evic_idx[3]	evic_op[2]	auto[0]	90	1		T19	1		T351	4		T363	1
evic_idx[3]	evic_op[2]	auto[1]	7	1		T24	1		T166	1		T205	1
evic_idx[3]	evic_op[2]	auto[2]	17	1		T5	1		T353	5		T354	1
evic_idx[3]	evic_op[2]	auto[3]	15	1		T279	1		T356	1		T364	1