Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17518	1		T333	8330		T334	9188		-	-
rd_lvl[2]	39050	1		T31	1143		T335	6270		T336	5530
rd_lvl[3]	23255	1		T31	1382		T335	337		T337	2871
rd_lvl[4]	38733	1		T31	305		T272	3250		T337	1754
rd_lvl[5]	15601	1		T31	918		T237	973		T307	1496
rd_lvl[6]	12167	1		T31	557		T237	1557		T307	832
rd_lvl[7]	7355	1		T31	424		T237	567		T272	56
rd_lvl[8]	13475	1		T31	423		T237	36		T313	1476
rd_lvl[9]	9627	1		T31	423		T32	247		T266	421
rd_lvl[10]	5443	1		T32	849		T30	523		T266	683
rd_lvl[11]	2856	1		T237	36		T30	382		T338	389
rd_lvl[12]	5193	1		T31	55		T29	296		T339	582
rd_lvl[13]	6090	1		T31	55		T29	590		T339	262
rd_lvl[14]	5198	1		T265	646		T340	438		T341	36
rd_lvl[15]	5703	1		T28	540		T29	79		T265	509