Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	309897	1		T1	2		T2	2		T3	1
all_pins[1]	309897	1		T1	2		T2	2		T3	1
all_pins[2]	309897	1		T1	2		T2	2		T3	1
all_pins[3]	309897	1		T1	2		T2	2		T3	1
all_pins[4]	309897	1		T1	2		T2	2		T3	1
all_pins[5]	309897	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1539804	1		T1	12		T2	12		T3	6
values[0x1]	319578	1		T22	1133		T25	1185		T31	6731
transitions[0x0=>0x1]	286744	1		T22	1133		T25	1185		T31	5817
transitions[0x1=>0x0]	286728	1		T22	1133		T25	1185		T31	5817

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	309722	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	175	1		T250	4		T251	7		T325	2
all_pins[0]	transitions[0x0=>0x1]	86	1		T250	3		T251	3		T325	2
all_pins[0]	transitions[0x1=>0x0]	70	1		T325	3		T326	1		T327	1
all_pins[1]	values[0x0]	309738	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	159	1		T250	1		T251	4		T325	3
all_pins[1]	transitions[0x0=>0x1]	130	1		T250	1		T251	4		T325	2
all_pins[1]	transitions[0x1=>0x0]	2704	1		T28	238		T265	8		T365	37
all_pins[2]	values[0x0]	307164	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2733	1		T28	238		T265	8		T365	37
all_pins[2]	transitions[0x0=>0x1]	40	1		T325	2		T326	1		T328	1
all_pins[2]	transitions[0x1=>0x0]	207757	1		T31	5685		T32	1096		T28	540
all_pins[3]	values[0x0]	99447	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	210450	1		T31	5685		T32	1096		T28	778
all_pins[3]	transitions[0x0=>0x1]	180479	1		T31	4771		T32	1096		T28	540
all_pins[3]	transitions[0x1=>0x0]	76030	1		T22	1133		T25	1185		T31	132
all_pins[4]	values[0x0]	203896	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	106001	1		T22	1133		T25	1185		T31	1046
all_pins[4]	transitions[0x0=>0x1]	105985	1		T22	1133		T25	1185		T31	1046
all_pins[4]	transitions[0x1=>0x0]	44	1		T250	2		T251	2		T326	2
all_pins[5]	values[0x0]	309837	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	60	1		T250	2		T251	2		T326	2
all_pins[5]	transitions[0x0=>0x1]	24	1		T251	1		T326	1		T329	1
all_pins[5]	transitions[0x1=>0x0]	123	1		T250	1		T251	5		T325	2