Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T250	4		T251	7		T325	4
all_values[1]	281	1		T250	4		T251	7		T325	4
all_values[2]	281	1		T250	4		T251	7		T325	4
all_values[3]	281	1		T250	4		T251	7		T325	4
all_values[4]	281	1		T250	4		T251	7		T325	4
all_values[5]	281	1		T250	4		T251	7		T325	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	951	1		T250	16		T251	24		T325	8
auto[1]	735	1		T250	8		T251	18		T325	16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	547	1		T250	10		T251	14		T325	7
auto[1]	1139	1		T250	14		T251	28		T325	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1004	1		T250	15		T251	26		T325	13
auto[1]	682	1		T250	9		T251	16		T325	11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	84	1		T250	1		T325	1		T326	1
all_values[0]	auto[0]	auto[1]	auto[1]	91	1		T250	1		T251	5		T325	1
all_values[0]	auto[1]	auto[0]	auto[1]	53	1		T250	1		T325	1		T326	2
all_values[0]	auto[1]	auto[1]	auto[1]	53	1		T250	1		T251	2		T325	1
all_values[1]	auto[0]	auto[0]	auto[1]	87	1		T250	2		T251	1		T327	1
all_values[1]	auto[0]	auto[1]	auto[1]	74	1		T251	2		T325	1		T326	2
all_values[1]	auto[1]	auto[0]	auto[1]	72	1		T250	2		T251	3		T325	2
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T251	1		T325	1		T327	3
all_values[2]	auto[0]	auto[0]	auto[0]	88	1		T250	2		T251	4		T326	2
all_values[2]	auto[0]	auto[1]	auto[0]	73	1		T325	1		T327	3		T328	1
all_values[2]	auto[1]	auto[0]	auto[1]	64	1		T250	2		T251	3		T328	2
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T325	3		T326	2		T327	1
all_values[3]	auto[0]	auto[0]	auto[0]	91	1		T250	1		T251	3		T326	1
all_values[3]	auto[0]	auto[1]	auto[0]	75	1		T250	1		T251	2		T325	4
all_values[3]	auto[1]	auto[0]	auto[1]	70	1		T250	1		T251	2		T326	2
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T250	1		T327	2		T329	1
all_values[4]	auto[0]	auto[0]	auto[0]	75	1		T250	4		T251	3		T326	2
all_values[4]	auto[0]	auto[0]	auto[1]	39	1		T325	2		T330	1		T331	4
all_values[4]	auto[0]	auto[1]	auto[0]	37	1		T251	1		T327	1		T329	1
all_values[4]	auto[0]	auto[1]	auto[1]	22	1		T251	1		T328	1		T332	2
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T251	1		T326	1		T327	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T251	1		T325	2		T326	1
all_values[5]	auto[0]	auto[0]	auto[0]	61	1		T327	2		T328	1		T329	2
all_values[5]	auto[0]	auto[0]	auto[1]	38	1		T251	2		T325	1		T327	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T250	2		T251	1		T325	2
all_values[5]	auto[0]	auto[1]	auto[1]	22	1		T250	1		T251	1		T326	1
all_values[5]	auto[1]	auto[0]	auto[1]	68	1		T251	2		T325	1		T326	1
all_values[5]	auto[1]	auto[1]	auto[1]	45	1		T250	1		T251	1		T326	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal