| T1077 |
/workspace/coverage/default/3.flash_ctrl_rand_ops.1363058184 |
|
|
Apr 15 02:37:28 PM PDT 24 |
Apr 15 02:49:29 PM PDT 24 |
174878600 ps |
| T1078 |
/workspace/coverage/default/0.flash_ctrl_host_dir_rd.2607569490 |
|
|
Apr 15 02:35:15 PM PDT 24 |
Apr 15 02:37:17 PM PDT 24 |
255685900 ps |
| T1079 |
/workspace/coverage/default/37.flash_ctrl_smoke.107961855 |
|
|
Apr 15 02:45:09 PM PDT 24 |
Apr 15 02:46:27 PM PDT 24 |
24977000 ps |
| T1080 |
/workspace/coverage/default/15.flash_ctrl_smoke.3486692294 |
|
|
Apr 15 02:42:05 PM PDT 24 |
Apr 15 02:43:45 PM PDT 24 |
19156000 ps |
| T1081 |
/workspace/coverage/default/3.flash_ctrl_rw_serr.2120142652 |
|
|
Apr 15 02:37:49 PM PDT 24 |
Apr 15 02:48:51 PM PDT 24 |
3460945600 ps |
| T1082 |
/workspace/coverage/default/58.flash_ctrl_connect.3586555781 |
|
|
Apr 15 02:46:15 PM PDT 24 |
Apr 15 02:46:29 PM PDT 24 |
32630600 ps |
| T1083 |
/workspace/coverage/default/19.flash_ctrl_sec_info_access.417691694 |
|
|
Apr 15 02:43:15 PM PDT 24 |
Apr 15 02:44:30 PM PDT 24 |
2098871900 ps |
| T1084 |
/workspace/coverage/default/9.flash_ctrl_prog_reset.2359008786 |
|
|
Apr 15 02:40:36 PM PDT 24 |
Apr 15 02:40:52 PM PDT 24 |
53194200 ps |
| T1085 |
/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3111398054 |
|
|
Apr 15 02:40:42 PM PDT 24 |
Apr 15 02:41:56 PM PDT 24 |
4623423400 ps |
| T1086 |
/workspace/coverage/default/44.flash_ctrl_sec_info_access.2072613232 |
|
|
Apr 15 02:45:47 PM PDT 24 |
Apr 15 02:46:55 PM PDT 24 |
7116695600 ps |
| T1087 |
/workspace/coverage/default/38.flash_ctrl_smoke.991849210 |
|
|
Apr 15 02:45:20 PM PDT 24 |
Apr 15 02:46:12 PM PDT 24 |
71898400 ps |
| T209 |
/workspace/coverage/default/2.flash_ctrl_rw_serr.2005082424 |
|
|
Apr 15 02:37:06 PM PDT 24 |
Apr 15 02:45:55 PM PDT 24 |
7744804600 ps |
| T1088 |
/workspace/coverage/default/3.flash_ctrl_alert_test.3463966059 |
|
|
Apr 15 02:38:10 PM PDT 24 |
Apr 15 02:38:24 PM PDT 24 |
46457000 ps |
| T1089 |
/workspace/coverage/default/0.flash_ctrl_ro_serr.1472551228 |
|
|
Apr 15 02:35:27 PM PDT 24 |
Apr 15 02:37:29 PM PDT 24 |
1332799400 ps |
| T1090 |
/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2859959293 |
|
|
Apr 15 02:43:01 PM PDT 24 |
Apr 15 02:43:15 PM PDT 24 |
19201100 ps |
| T1091 |
/workspace/coverage/default/45.flash_ctrl_smoke.2185464821 |
|
|
Apr 15 02:45:47 PM PDT 24 |
Apr 15 02:47:27 PM PDT 24 |
41195800 ps |
| T1092 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3678818591 |
|
|
Apr 15 02:42:36 PM PDT 24 |
Apr 15 02:44:42 PM PDT 24 |
13541866100 ps |
| T1093 |
/workspace/coverage/default/33.flash_ctrl_disable.3283875151 |
|
|
Apr 15 02:44:54 PM PDT 24 |
Apr 15 02:45:16 PM PDT 24 |
17425700 ps |
| T1094 |
/workspace/coverage/default/10.flash_ctrl_connect.1977513461 |
|
|
Apr 15 02:40:52 PM PDT 24 |
Apr 15 02:41:06 PM PDT 24 |
59147300 ps |
| T1095 |
/workspace/coverage/default/38.flash_ctrl_disable.396990152 |
|
|
Apr 15 02:45:26 PM PDT 24 |
Apr 15 02:45:48 PM PDT 24 |
20430700 ps |
| T1096 |
/workspace/coverage/default/6.flash_ctrl_intr_wr.2956830096 |
|
|
Apr 15 02:39:21 PM PDT 24 |
Apr 15 02:41:10 PM PDT 24 |
9785798700 ps |
| T1097 |
/workspace/coverage/default/25.flash_ctrl_sec_info_access.1781964911 |
|
|
Apr 15 02:44:01 PM PDT 24 |
Apr 15 02:45:10 PM PDT 24 |
1437267500 ps |
| T1098 |
/workspace/coverage/default/28.flash_ctrl_prog_reset.230724251 |
|
|
Apr 15 02:44:21 PM PDT 24 |
Apr 15 02:44:34 PM PDT 24 |
55259600 ps |
| T1099 |
/workspace/coverage/default/4.flash_ctrl_re_evict.3362136943 |
|
|
Apr 15 02:38:26 PM PDT 24 |
Apr 15 02:39:06 PM PDT 24 |
260396100 ps |
| T1100 |
/workspace/coverage/default/14.flash_ctrl_prog_reset.3693391339 |
|
|
Apr 15 02:41:58 PM PDT 24 |
Apr 15 02:42:13 PM PDT 24 |
77834700 ps |
| T47 |
/workspace/coverage/default/2.flash_ctrl_access_after_disable.2081989205 |
|
|
Apr 15 02:37:23 PM PDT 24 |
Apr 15 02:37:37 PM PDT 24 |
102914500 ps |
| T1101 |
/workspace/coverage/default/9.flash_ctrl_error_prog_win.1165022794 |
|
|
Apr 15 02:40:27 PM PDT 24 |
Apr 15 02:56:04 PM PDT 24 |
1382582700 ps |
| T1102 |
/workspace/coverage/default/12.flash_ctrl_rand_ops.1935480355 |
|
|
Apr 15 02:41:18 PM PDT 24 |
Apr 15 02:47:24 PM PDT 24 |
83112800 ps |
| T1103 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3857006657 |
|
|
Apr 15 02:39:21 PM PDT 24 |
Apr 15 02:45:14 PM PDT 24 |
50161024300 ps |
| T419 |
/workspace/coverage/default/2.flash_ctrl_invalid_op.1744821228 |
|
|
Apr 15 02:36:57 PM PDT 24 |
Apr 15 02:38:31 PM PDT 24 |
981105100 ps |
| T1104 |
/workspace/coverage/default/12.flash_ctrl_ro.3924053795 |
|
|
Apr 15 02:41:27 PM PDT 24 |
Apr 15 02:43:22 PM PDT 24 |
1839243500 ps |
| T1105 |
/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.2179602512 |
|
|
Apr 15 02:36:27 PM PDT 24 |
Apr 15 02:36:50 PM PDT 24 |
18567200 ps |
| T1106 |
/workspace/coverage/default/38.flash_ctrl_alert_test.2175032939 |
|
|
Apr 15 02:45:25 PM PDT 24 |
Apr 15 02:45:39 PM PDT 24 |
63618800 ps |
| T1107 |
/workspace/coverage/default/29.flash_ctrl_alert_test.3951841817 |
|
|
Apr 15 02:44:32 PM PDT 24 |
Apr 15 02:44:46 PM PDT 24 |
16976100 ps |
| T420 |
/workspace/coverage/default/7.flash_ctrl_invalid_op.1409804279 |
|
|
Apr 15 02:39:39 PM PDT 24 |
Apr 15 02:41:15 PM PDT 24 |
4056798400 ps |
| T1108 |
/workspace/coverage/default/7.flash_ctrl_ro.83074599 |
|
|
Apr 15 02:39:43 PM PDT 24 |
Apr 15 02:41:13 PM PDT 24 |
387808900 ps |
| T1109 |
/workspace/coverage/default/13.flash_ctrl_smoke.3656951611 |
|
|
Apr 15 02:41:40 PM PDT 24 |
Apr 15 02:45:16 PM PDT 24 |
39378000 ps |
| T1110 |
/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2025214881 |
|
|
Apr 15 02:42:30 PM PDT 24 |
Apr 15 02:42:44 PM PDT 24 |
25608700 ps |
| T1111 |
/workspace/coverage/default/4.flash_ctrl_serr_counter.362700697 |
|
|
Apr 15 02:38:19 PM PDT 24 |
Apr 15 02:39:33 PM PDT 24 |
640995600 ps |
| T1112 |
/workspace/coverage/default/26.flash_ctrl_intr_rd.1610311233 |
|
|
Apr 15 02:44:03 PM PDT 24 |
Apr 15 02:47:04 PM PDT 24 |
4466771300 ps |
| T1113 |
/workspace/coverage/default/32.flash_ctrl_otp_reset.775030906 |
|
|
Apr 15 02:44:43 PM PDT 24 |
Apr 15 02:46:56 PM PDT 24 |
79038800 ps |
| T1114 |
/workspace/coverage/default/4.flash_ctrl_smoke_hw.1402134539 |
|
|
Apr 15 02:38:10 PM PDT 24 |
Apr 15 02:38:36 PM PDT 24 |
17474300 ps |
| T1115 |
/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1369356583 |
|
|
Apr 15 02:41:22 PM PDT 24 |
Apr 15 02:55:43 PM PDT 24 |
350270340400 ps |
| T204 |
/workspace/coverage/default/8.flash_ctrl_rw_derr.87987369 |
|
|
Apr 15 02:40:08 PM PDT 24 |
Apr 15 02:51:10 PM PDT 24 |
8253447400 ps |
| T1116 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3089040198 |
|
|
Apr 15 02:40:55 PM PDT 24 |
Apr 15 02:42:45 PM PDT 24 |
10034904400 ps |
| T1117 |
/workspace/coverage/default/26.flash_ctrl_disable.2121647556 |
|
|
Apr 15 02:44:05 PM PDT 24 |
Apr 15 02:44:28 PM PDT 24 |
20733100 ps |
| T1118 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.4156800503 |
|
|
Apr 15 02:35:14 PM PDT 24 |
Apr 15 02:37:45 PM PDT 24 |
77544500 ps |
| T1119 |
/workspace/coverage/default/14.flash_ctrl_rw.1373520343 |
|
|
Apr 15 02:41:54 PM PDT 24 |
Apr 15 02:49:34 PM PDT 24 |
3432334000 ps |
| T1120 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.503499863 |
|
|
Apr 15 02:44:26 PM PDT 24 |
Apr 15 02:48:40 PM PDT 24 |
33807642100 ps |
| T1121 |
/workspace/coverage/default/0.flash_ctrl_wo.3253564651 |
|
|
Apr 15 02:35:26 PM PDT 24 |
Apr 15 02:37:37 PM PDT 24 |
1537482800 ps |
| T1122 |
/workspace/coverage/default/35.flash_ctrl_sec_info_access.4221795473 |
|
|
Apr 15 02:45:01 PM PDT 24 |
Apr 15 02:46:13 PM PDT 24 |
3009598100 ps |
| T1123 |
/workspace/coverage/default/47.flash_ctrl_disable.3495533465 |
|
|
Apr 15 02:45:55 PM PDT 24 |
Apr 15 02:46:18 PM PDT 24 |
13944000 ps |
| T1124 |
/workspace/coverage/default/2.flash_ctrl_rw.1814389084 |
|
|
Apr 15 02:37:06 PM PDT 24 |
Apr 15 02:45:35 PM PDT 24 |
9670717500 ps |
| T1125 |
/workspace/coverage/default/3.flash_ctrl_host_dir_rd.3605693296 |
|
|
Apr 15 02:37:30 PM PDT 24 |
Apr 15 02:38:18 PM PDT 24 |
31166900 ps |
| T348 |
/workspace/coverage/default/12.flash_ctrl_re_evict.1617101809 |
|
|
Apr 15 02:41:34 PM PDT 24 |
Apr 15 02:42:08 PM PDT 24 |
146403500 ps |
| T334 |
/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2973250608 |
|
|
Apr 15 02:39:44 PM PDT 24 |
Apr 15 02:45:14 PM PDT 24 |
8594317800 ps |
| T1126 |
/workspace/coverage/default/41.flash_ctrl_otp_reset.343148113 |
|
|
Apr 15 02:45:44 PM PDT 24 |
Apr 15 02:47:54 PM PDT 24 |
200425300 ps |
| T1127 |
/workspace/coverage/default/59.flash_ctrl_connect.825039818 |
|
|
Apr 15 02:46:14 PM PDT 24 |
Apr 15 02:46:28 PM PDT 24 |
13497300 ps |
| T1128 |
/workspace/coverage/default/47.flash_ctrl_sec_info_access.2026946241 |
|
|
Apr 15 02:45:56 PM PDT 24 |
Apr 15 02:47:08 PM PDT 24 |
3073856400 ps |
| T1129 |
/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2844199372 |
|
|
Apr 15 02:38:38 PM PDT 24 |
Apr 15 02:43:37 PM PDT 24 |
10011902300 ps |
| T1130 |
/workspace/coverage/default/1.flash_ctrl_sec_info_access.419166734 |
|
|
Apr 15 02:36:31 PM PDT 24 |
Apr 15 02:37:36 PM PDT 24 |
2904498500 ps |
| T1131 |
/workspace/coverage/default/2.flash_ctrl_error_prog_win.2430734355 |
|
|
Apr 15 02:36:55 PM PDT 24 |
Apr 15 02:50:12 PM PDT 24 |
672349200 ps |
| T1132 |
/workspace/coverage/default/9.flash_ctrl_rand_ops.109647366 |
|
|
Apr 15 02:40:20 PM PDT 24 |
Apr 15 02:48:57 PM PDT 24 |
518955500 ps |
| T38 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2970581359 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:44:02 PM PDT 24 |
781934700 ps |
| T39 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3948194204 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:43:51 PM PDT 24 |
1974264700 ps |
| T40 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1157422874 |
|
|
Apr 15 12:37:38 PM PDT 24 |
Apr 15 12:45:11 PM PDT 24 |
358432700 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3013758215 |
|
|
Apr 15 12:37:26 PM PDT 24 |
Apr 15 12:37:57 PM PDT 24 |
47048400 ps |
| T243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.673147348 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
60735700 ps |
| T250 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.392517527 |
|
|
Apr 15 12:37:46 PM PDT 24 |
Apr 15 12:38:00 PM PDT 24 |
73964400 ps |
| T193 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.512461388 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
49169900 ps |
| T199 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.4099801560 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:52:19 PM PDT 24 |
1553518200 ps |
| T198 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.728479409 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:45:18 PM PDT 24 |
353302000 ps |
| T194 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3128076318 |
|
|
Apr 15 12:37:03 PM PDT 24 |
Apr 15 12:37:22 PM PDT 24 |
54510700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1086002260 |
|
|
Apr 15 12:37:08 PM PDT 24 |
Apr 15 12:37:25 PM PDT 24 |
24040100 ps |
| T195 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1653131240 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
104947600 ps |
| T1134 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.902615995 |
|
|
Apr 15 12:37:40 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
23827900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.401540970 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
19749200 ps |
| T196 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3985184384 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
126132200 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.789239918 |
|
|
Apr 15 12:37:09 PM PDT 24 |
Apr 15 12:37:23 PM PDT 24 |
26423600 ps |
| T251 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2604502527 |
|
|
Apr 15 12:37:45 PM PDT 24 |
Apr 15 12:38:00 PM PDT 24 |
22082700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3690952935 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
31416300 ps |
| T197 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.630149780 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
119889100 ps |
| T325 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2988444309 |
|
|
Apr 15 12:37:44 PM PDT 24 |
Apr 15 12:37:59 PM PDT 24 |
55818900 ps |
| T227 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3325169912 |
|
|
Apr 15 12:37:22 PM PDT 24 |
Apr 15 12:50:02 PM PDT 24 |
1317033600 ps |
| T326 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3721060359 |
|
|
Apr 15 12:37:42 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
24710700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.13966668 |
|
|
Apr 15 12:37:27 PM PDT 24 |
Apr 15 12:38:44 PM PDT 24 |
2194107500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4251669080 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:44 PM PDT 24 |
57402100 ps |
| T244 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2118225584 |
|
|
Apr 15 12:37:40 PM PDT 24 |
Apr 15 12:37:57 PM PDT 24 |
75551000 ps |
| T1140 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1742694558 |
|
|
Apr 15 12:37:10 PM PDT 24 |
Apr 15 12:37:24 PM PDT 24 |
15883800 ps |
| T245 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3671207404 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
620158500 ps |
| T327 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2826618250 |
|
|
Apr 15 12:37:46 PM PDT 24 |
Apr 15 12:38:01 PM PDT 24 |
15778800 ps |
| T328 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1597623041 |
|
|
Apr 15 12:37:22 PM PDT 24 |
Apr 15 12:37:36 PM PDT 24 |
55117400 ps |
| T224 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.492614009 |
|
|
Apr 15 12:37:09 PM PDT 24 |
Apr 15 12:37:29 PM PDT 24 |
82130300 ps |
| T225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3374901972 |
|
|
Apr 15 12:37:42 PM PDT 24 |
Apr 15 12:38:00 PM PDT 24 |
147025100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4243525973 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
50656300 ps |
| T329 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3394389382 |
|
|
Apr 15 12:37:43 PM PDT 24 |
Apr 15 12:37:57 PM PDT 24 |
58134200 ps |
| T1142 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.341898244 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
13095800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2663033968 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
41448700 ps |
| T231 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3576202162 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
16739900 ps |
| T1144 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4179932287 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
26085200 ps |
| T226 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1239312109 |
|
|
Apr 15 12:37:13 PM PDT 24 |
Apr 15 12:37:33 PM PDT 24 |
205108000 ps |
| T1145 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2548418004 |
|
|
Apr 15 12:37:08 PM PDT 24 |
Apr 15 12:37:22 PM PDT 24 |
12509600 ps |
| T1146 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2839477410 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
66154100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1292186230 |
|
|
Apr 15 12:37:40 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
150096500 ps |
| T330 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2458202730 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:44 PM PDT 24 |
32267900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3781489596 |
|
|
Apr 15 12:37:14 PM PDT 24 |
Apr 15 12:37:28 PM PDT 24 |
15149500 ps |
| T228 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4237062145 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:52:30 PM PDT 24 |
554268200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2387505639 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:38:12 PM PDT 24 |
453101300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2983182570 |
|
|
Apr 15 12:37:01 PM PDT 24 |
Apr 15 12:37:33 PM PDT 24 |
21554600 ps |
| T301 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.15399304 |
|
|
Apr 15 12:37:05 PM PDT 24 |
Apr 15 12:38:12 PM PDT 24 |
3271030000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.275815053 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
154979100 ps |
| T1152 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4000041240 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
72055000 ps |
| T331 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1276899160 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
17072700 ps |
| T230 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2265603427 |
|
|
Apr 15 12:37:47 PM PDT 24 |
Apr 15 12:52:38 PM PDT 24 |
1377599200 ps |
| T1153 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3632552665 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
54828000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1540516312 |
|
|
Apr 15 12:37:19 PM PDT 24 |
Apr 15 12:37:59 PM PDT 24 |
1220163600 ps |
| T1155 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3430596623 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
39899100 ps |
| T229 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3882376406 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
276435300 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1218322215 |
|
|
Apr 15 12:37:05 PM PDT 24 |
Apr 15 12:37:20 PM PDT 24 |
71668100 ps |
| T261 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.106508099 |
|
|
Apr 15 12:37:27 PM PDT 24 |
Apr 15 12:37:46 PM PDT 24 |
173003300 ps |
| T332 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3915113872 |
|
|
Apr 15 12:37:40 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
58577500 ps |
| T258 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2783690052 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
111982000 ps |
| T1156 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2413907362 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
21043900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3003981087 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:38:09 PM PDT 24 |
64065200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3547705350 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
102365400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2256861911 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:38:00 PM PDT 24 |
124532500 ps |
| T1160 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2156355100 |
|
|
Apr 15 12:37:45 PM PDT 24 |
Apr 15 12:38:02 PM PDT 24 |
162958100 ps |
| T293 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1221336749 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:38:12 PM PDT 24 |
833614800 ps |
| T1161 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1133792615 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
44437800 ps |
| T1162 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2191376302 |
|
|
Apr 15 12:37:12 PM PDT 24 |
Apr 15 12:37:32 PM PDT 24 |
86001000 ps |
| T1163 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2353393150 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
327648500 ps |
| T1164 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3155962795 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
24796300 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3361155781 |
|
|
Apr 15 12:37:24 PM PDT 24 |
Apr 15 12:37:42 PM PDT 24 |
87077400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2016557964 |
|
|
Apr 15 12:37:28 PM PDT 24 |
Apr 15 12:37:42 PM PDT 24 |
13117500 ps |
| T1166 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3282624422 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
17769900 ps |
| T1167 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3878531418 |
|
|
Apr 15 12:37:39 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
28740200 ps |
| T260 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1832389846 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
70920700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1269530416 |
|
|
Apr 15 12:37:07 PM PDT 24 |
Apr 15 12:37:26 PM PDT 24 |
65647500 ps |
| T294 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2876837323 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:50:04 PM PDT 24 |
2594081000 ps |
| T295 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3583532804 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
484396400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3723714184 |
|
|
Apr 15 12:37:38 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
22724900 ps |
| T1170 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3944747143 |
|
|
Apr 15 12:37:10 PM PDT 24 |
Apr 15 12:37:27 PM PDT 24 |
163270500 ps |
| T1171 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1422151901 |
|
|
Apr 15 12:37:06 PM PDT 24 |
Apr 15 12:37:25 PM PDT 24 |
56711700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2459374246 |
|
|
Apr 15 12:37:09 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
2895626700 ps |
| T367 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3118234836 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:45:13 PM PDT 24 |
359132000 ps |
| T371 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3397554758 |
|
|
Apr 15 12:37:02 PM PDT 24 |
Apr 15 12:51:55 PM PDT 24 |
1434047900 ps |
| T1173 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1858930088 |
|
|
Apr 15 12:37:43 PM PDT 24 |
Apr 15 12:37:58 PM PDT 24 |
55915200 ps |
| T255 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2205111755 |
|
|
Apr 15 12:37:43 PM PDT 24 |
Apr 15 12:38:03 PM PDT 24 |
62169800 ps |
| T296 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2631520238 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:52:30 PM PDT 24 |
1035257100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2575763116 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
62520500 ps |
| T297 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2292535922 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
59411500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3559464738 |
|
|
Apr 15 12:37:24 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
42528500 ps |
| T1176 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2048134415 |
|
|
Apr 15 12:37:22 PM PDT 24 |
Apr 15 12:37:39 PM PDT 24 |
13764300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3554525504 |
|
|
Apr 15 12:37:41 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
18685800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4162268143 |
|
|
Apr 15 12:37:25 PM PDT 24 |
Apr 15 12:37:39 PM PDT 24 |
214225600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2485476785 |
|
|
Apr 15 12:37:38 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
62618600 ps |
| T1180 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1151875881 |
|
|
Apr 15 12:37:38 PM PDT 24 |
Apr 15 12:38:12 PM PDT 24 |
64000200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4012300236 |
|
|
Apr 15 12:37:45 PM PDT 24 |
Apr 15 12:37:59 PM PDT 24 |
16504800 ps |
| T298 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2033258048 |
|
|
Apr 15 12:37:24 PM PDT 24 |
Apr 15 12:38:09 PM PDT 24 |
53002400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.535246888 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
486336400 ps |
| T1183 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2272367621 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:38:22 PM PDT 24 |
415112700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2681328 |
|
|
Apr 15 12:37:03 PM PDT 24 |
Apr 15 12:37:19 PM PDT 24 |
15223500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3626559363 |
|
|
Apr 15 12:37:03 PM PDT 24 |
Apr 15 12:38:21 PM PDT 24 |
2195227400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3318090743 |
|
|
Apr 15 12:37:28 PM PDT 24 |
Apr 15 12:37:42 PM PDT 24 |
163029800 ps |
| T299 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.887891598 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
174045100 ps |
| T1187 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2377557543 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
20547300 ps |
| T1188 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2478685075 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
28847900 ps |
| T302 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.612673434 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
102868500 ps |
| T1189 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.210353452 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
24331500 ps |
| T1190 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.806607270 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
23642800 ps |
| T259 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4150339409 |
|
|
Apr 15 12:37:41 PM PDT 24 |
Apr 15 12:52:32 PM PDT 24 |
699521000 ps |
| T252 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1235273836 |
|
|
Apr 15 12:37:38 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
31243200 ps |
| T300 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1114145807 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:38:08 PM PDT 24 |
276311500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1882753269 |
|
|
Apr 15 12:37:39 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
146624400 ps |
| T1192 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1803955773 |
|
|
Apr 15 12:37:01 PM PDT 24 |
Apr 15 12:37:15 PM PDT 24 |
33471100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4124181021 |
|
|
Apr 15 12:37:15 PM PDT 24 |
Apr 15 12:37:28 PM PDT 24 |
52512500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.432038501 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:44 PM PDT 24 |
172153000 ps |
| T256 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2153731376 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
30745400 ps |
| T264 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2173191547 |
|
|
Apr 15 12:37:28 PM PDT 24 |
Apr 15 12:52:26 PM PDT 24 |
1659449600 ps |
| T257 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3725165041 |
|
|
Apr 15 12:37:29 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
273878300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1074073586 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
26918700 ps |
| T1196 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3384192166 |
|
|
Apr 15 12:37:39 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
30255100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1597207792 |
|
|
Apr 15 12:37:29 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
91419800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.694813155 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
17820400 ps |
| T303 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3627786673 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
400047500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1478571235 |
|
|
Apr 15 12:37:49 PM PDT 24 |
Apr 15 12:38:04 PM PDT 24 |
16703300 ps |
| T1200 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.115408807 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
13909700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2888798708 |
|
|
Apr 15 12:37:39 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
76070800 ps |
| T1202 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1515119551 |
|
|
Apr 15 12:37:06 PM PDT 24 |
Apr 15 12:37:23 PM PDT 24 |
109295700 ps |
| T233 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2907304144 |
|
|
Apr 15 12:37:29 PM PDT 24 |
Apr 15 12:37:43 PM PDT 24 |
21352600 ps |
| T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.641468892 |
|
|
Apr 15 12:37:05 PM PDT 24 |
Apr 15 12:37:20 PM PDT 24 |
23953600 ps |
| T1204 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1596575728 |
|
|
Apr 15 12:37:38 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
24450100 ps |
| T1205 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3938566854 |
|
|
Apr 15 12:37:29 PM PDT 24 |
Apr 15 12:38:12 PM PDT 24 |
1287277900 ps |
| T1206 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3074052249 |
|
|
Apr 15 12:37:45 PM PDT 24 |
Apr 15 12:37:59 PM PDT 24 |
17359400 ps |
| T1207 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2483373012 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
12968400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1596038348 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
39547800 ps |
| T1209 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.129801375 |
|
|
Apr 15 12:37:40 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
52910700 ps |
| T1210 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2028358146 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
422584200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4279721951 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
54534300 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1482941319 |
|
|
Apr 15 12:37:24 PM PDT 24 |
Apr 15 12:37:39 PM PDT 24 |
28503300 ps |
| T253 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2333384365 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
160908000 ps |
| T1212 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2367572725 |
|
|
Apr 15 12:37:29 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
224056900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2468186418 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:50 PM PDT 24 |
226220800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.152658890 |
|
|
Apr 15 12:37:39 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
17724100 ps |
| T1215 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3597162296 |
|
|
Apr 15 12:37:44 PM PDT 24 |
Apr 15 12:38:03 PM PDT 24 |
170436600 ps |
| T254 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3904894452 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
193198300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3682110348 |
|
|
Apr 15 12:37:20 PM PDT 24 |
Apr 15 12:37:36 PM PDT 24 |
23200900 ps |
| T1217 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3218257200 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
43037400 ps |
| T1218 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1944876182 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
482026000 ps |
| T262 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.421295649 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
64948700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1471758859 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
24306100 ps |
| T1220 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2527809630 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:44 PM PDT 24 |
15763600 ps |
| T1221 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.622383561 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:38:05 PM PDT 24 |
126805900 ps |
| T1222 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3270203424 |
|
|
Apr 15 12:37:14 PM PDT 24 |
Apr 15 12:37:30 PM PDT 24 |
50468200 ps |
| T368 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.836311107 |
|
|
Apr 15 12:37:09 PM PDT 24 |
Apr 15 12:44:42 PM PDT 24 |
451230700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.871616009 |
|
|
Apr 15 12:37:14 PM PDT 24 |
Apr 15 12:38:39 PM PDT 24 |
3281745300 ps |
| T1224 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2326558265 |
|
|
Apr 15 12:37:39 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
27405300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.948518570 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:37:46 PM PDT 24 |
32778500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3528027565 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:37:48 PM PDT 24 |
30712500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2536096009 |
|
|
Apr 15 12:37:10 PM PDT 24 |
Apr 15 12:37:27 PM PDT 24 |
18738400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4102096072 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
23640200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1023322185 |
|
|
Apr 15 12:37:31 PM PDT 24 |
Apr 15 12:38:03 PM PDT 24 |
398386800 ps |
| T1230 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2364123964 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:49 PM PDT 24 |
98526600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.599599934 |
|
|
Apr 15 12:37:28 PM PDT 24 |
Apr 15 12:37:45 PM PDT 24 |
43212200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.118098657 |
|
|
Apr 15 12:37:08 PM PDT 24 |
Apr 15 12:37:23 PM PDT 24 |
49637500 ps |
| T1233 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1821849044 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:51 PM PDT 24 |
18821800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3776703771 |
|
|
Apr 15 12:37:42 PM PDT 24 |
Apr 15 12:37:56 PM PDT 24 |
56361500 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1319191106 |
|
|
Apr 15 12:37:07 PM PDT 24 |
Apr 15 12:37:26 PM PDT 24 |
18120700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2907649001 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:47 PM PDT 24 |
606137500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.109082440 |
|
|
Apr 15 12:37:32 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
49785000 ps |
| T235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2202324257 |
|
|
Apr 15 12:37:20 PM PDT 24 |
Apr 15 12:37:34 PM PDT 24 |
48636800 ps |
| T1238 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1611959651 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
31883200 ps |
| T1239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1416563579 |
|
|
Apr 15 12:37:23 PM PDT 24 |
Apr 15 12:38:21 PM PDT 24 |
908502300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2944261247 |
|
|
Apr 15 12:37:43 PM PDT 24 |
Apr 15 12:38:04 PM PDT 24 |
61977000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1227297344 |
|
|
Apr 15 12:37:21 PM PDT 24 |
Apr 15 12:37:35 PM PDT 24 |
44662200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1980276888 |
|
|
Apr 15 12:37:41 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
55985100 ps |
| T1243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3379985883 |
|
|
Apr 15 12:37:05 PM PDT 24 |
Apr 15 12:37:21 PM PDT 24 |
317039200 ps |
| T373 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1341573839 |
|
|
Apr 15 12:37:35 PM PDT 24 |
Apr 15 12:52:19 PM PDT 24 |
2412699400 ps |
| T1244 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3891654932 |
|
|
Apr 15 12:37:28 PM PDT 24 |
Apr 15 12:37:46 PM PDT 24 |
76925500 ps |
| T1245 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4096333522 |
|
|
Apr 15 12:37:47 PM PDT 24 |
Apr 15 12:38:02 PM PDT 24 |
18196400 ps |
| T1246 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1016712734 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
121241200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.72175649 |
|
|
Apr 15 12:37:10 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
27011100 ps |
| T369 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.875469640 |
|
|
Apr 15 12:37:33 PM PDT 24 |
Apr 15 12:45:08 PM PDT 24 |
1578385200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4140658977 |
|
|
Apr 15 12:37:36 PM PDT 24 |
Apr 15 12:37:54 PM PDT 24 |
342768500 ps |
| T1249 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2595817043 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:52 PM PDT 24 |
66525500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2652915396 |
|
|
Apr 15 12:37:34 PM PDT 24 |
Apr 15 12:37:53 PM PDT 24 |
135241600 ps |
| T1251 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3895411560 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:43 PM PDT 24 |
208134100 ps |
| T1252 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2388894988 |
|
|
Apr 15 12:37:37 PM PDT 24 |
Apr 15 12:37:55 PM PDT 24 |
105573300 ps |
| T263 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1355837795 |
|
|
Apr 15 12:37:30 PM PDT 24 |
Apr 15 12:37:46 PM PDT 24 |
86999200 ps |
| T1253 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2963292333 |
|
|
Apr 15 12:37:41 PM PDT 24 |
Apr 15 12:37:57 PM PDT 24 |
13385700 ps |