Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333968	1		T1	1		T2	2		T3	1
all_values[1]	333968	1		T1	1		T2	2		T3	1
all_values[2]	333968	1		T1	1		T2	2		T3	1
all_values[3]	333968	1		T1	1		T2	2		T3	1
all_values[4]	333968	1		T1	1		T2	2		T3	1
all_values[5]	333968	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	674322	1		T1	6		T2	12		T3	6
auto[1]	1329486	1		T32	15956		T33	7248		T25	9568

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	985299	1		T1	4		T2	6		T3	4
auto[1]	1018509	1		T1	2		T2	6		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	333831	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	137	1		T259	2		T260	2		T261	2
all_values[1]	auto[0]	auto[1]	333819	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	149	1		T259	4		T260	1		T261	2
all_values[2]	auto[0]	auto[0]	1622	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	32	1		T260	1		T261	1		T319	1
all_values[2]	auto[1]	auto[0]	332251	1		T32	3989		T33	1812		T25	2392
all_values[2]	auto[1]	auto[1]	63	1		T259	1		T260	3		T261	1
all_values[3]	auto[0]	auto[0]	1629	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	51	1		T259	1		T260	3		T261	2
all_values[3]	auto[1]	auto[0]	80019	1		T32	180		T33	906		T25	1196
all_values[3]	auto[1]	auto[1]	252269	1		T32	3809		T33	906		T25	1196
all_values[4]	auto[0]	auto[0]	1139	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	522	1		T2	1		T4	1		T17	1
all_values[4]	auto[1]	auto[0]	234890	1		T32	3084		T33	906		T25	1196
all_values[4]	auto[1]	auto[1]	97417	1		T32	905		T33	906		T25	1196
all_values[5]	auto[0]	auto[0]	1532	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	145	1		T2	1		T34	1		T35	1
all_values[5]	auto[1]	auto[0]	332217	1		T32	3989		T33	1812		T25	2392
all_values[5]	auto[1]	auto[1]	74	1		T261	1		T319	3		T320	4