Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8706 |
1 |
|
T11 |
2 |
|
T40 |
5 |
|
T47 |
199 |
| others[1] |
996 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T56 |
1 |
| others[2] |
1036 |
1 |
|
T4 |
4 |
|
T40 |
1 |
|
T80 |
1 |
| others[3] |
1693 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T17 |
1 |
| false |
539 |
1 |
|
T1 |
1 |
|
T39 |
1 |
|
T106 |
10 |
| true |
1376 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T106 |
12 |
|
T43 |
1 |
|
T62 |
1 |
| others[1] |
228 |
1 |
|
T106 |
15 |
|
T82 |
12 |
|
T83 |
12 |
| others[2] |
222 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T106 |
8 |
| others[3] |
377 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T31 |
1 |
| false |
84 |
1 |
|
T6 |
1 |
|
T106 |
5 |
|
T121 |
1 |
| true |
13208 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T106 |
6 |
|
T82 |
12 |
|
T83 |
10 |
| others[1] |
196 |
1 |
|
T19 |
1 |
|
T106 |
17 |
|
T41 |
1 |
| others[2] |
193 |
1 |
|
T31 |
1 |
|
T106 |
9 |
|
T34 |
1 |
| others[3] |
344 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T53 |
1 |
| false |
112 |
1 |
|
T18 |
1 |
|
T106 |
6 |
|
T392 |
1 |
| true |
13299 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8861 |
1 |
|
T4 |
3 |
|
T11 |
2 |
|
T17 |
1 |
| others[1] |
1219 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T80 |
1 |
| others[2] |
1146 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T40 |
2 |
| others[3] |
2045 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T56 |
1 |
| false |
626 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T106 |
7 |
| true |
449 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8877 |
1 |
|
T4 |
4 |
|
T11 |
2 |
|
T40 |
1 |
| others[1] |
1235 |
1 |
|
T4 |
2 |
|
T40 |
4 |
|
T37 |
1 |
| others[2] |
1208 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T40 |
5 |
| others[3] |
1995 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T17 |
1 |
| false |
609 |
1 |
|
T17 |
1 |
|
T40 |
1 |
|
T31 |
1 |
| true |
422 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T19 |
1 |
|
T106 |
6 |
|
T392 |
1 |
| others[1] |
87 |
1 |
|
T31 |
1 |
|
T106 |
4 |
|
T392 |
1 |
| others[2] |
97 |
1 |
|
T17 |
1 |
|
T106 |
1 |
|
T391 |
1 |
| others[3] |
166 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T43 |
1 |
| false |
56 |
1 |
|
T106 |
1 |
|
T41 |
1 |
|
T204 |
1 |
| true |
13840 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T106 |
15 |
|
T224 |
1 |
|
T62 |
1 |
| others[1] |
195 |
1 |
|
T18 |
1 |
|
T106 |
7 |
|
T204 |
1 |
| others[2] |
231 |
1 |
|
T19 |
1 |
|
T106 |
9 |
|
T35 |
1 |
| others[3] |
350 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T53 |
1 |
| false |
122 |
1 |
|
T106 |
2 |
|
T41 |
1 |
|
T82 |
6 |
| true |
13239 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8617 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T11 |
2 |
| others[1] |
1007 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
1 |
| others[2] |
1060 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T56 |
1 |
| others[3] |
1706 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T40 |
7 |
| false |
518 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| true |
1438 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T5 |
1 |
|
T106 |
4 |
|
T388 |
1 |
| others[1] |
222 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T53 |
1 |
| others[2] |
202 |
1 |
|
T31 |
1 |
|
T106 |
8 |
|
T34 |
1 |
| others[3] |
367 |
1 |
|
T106 |
23 |
|
T43 |
1 |
|
T391 |
1 |
| false |
119 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T106 |
8 |
| true |
13227 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T106 |
7 |
| others[1] |
204 |
1 |
|
T18 |
1 |
|
T106 |
9 |
|
T224 |
1 |
| others[2] |
199 |
1 |
|
T5 |
1 |
|
T106 |
10 |
|
T82 |
4 |
| others[3] |
330 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T106 |
17 |
| false |
115 |
1 |
|
T106 |
5 |
|
T41 |
1 |
|
T222 |
1 |
| true |
13302 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8841 |
1 |
|
T4 |
2 |
|
T11 |
2 |
|
T47 |
199 |
| others[1] |
1213 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| others[2] |
1203 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T40 |
1 |
| others[3] |
2018 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T56 |
1 |
| false |
617 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T37 |
1 |
| true |
454 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1163 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
2 |
| others[1] |
1197 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T40 |
4 |
| others[2] |
1199 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
5 |
| others[3] |
2021 |
1 |
|
T4 |
2 |
|
T111 |
1 |
|
T40 |
3 |
| false |
679 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T40 |
1 |
| true |
425 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T106 |
3 |
|
T389 |
1 |
|
T394 |
1 |
| others[1] |
98 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T391 |
1 |
| others[2] |
91 |
1 |
|
T5 |
1 |
|
T106 |
3 |
|
T43 |
1 |
| others[3] |
183 |
1 |
|
T106 |
8 |
|
T41 |
1 |
|
T222 |
2 |
| false |
61 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T106 |
1 |
| true |
6161 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T106 |
10 |
|
T107 |
1 |
|
T222 |
2 |
| others[1] |
204 |
1 |
|
T20 |
1 |
|
T106 |
7 |
|
T25 |
1 |
| others[2] |
230 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T106 |
12 |
| others[3] |
383 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T106 |
14 |
| false |
126 |
1 |
|
T106 |
9 |
|
T224 |
1 |
|
T209 |
1 |
| true |
5499 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T40 |
4 |
| others[1] |
1010 |
1 |
|
T4 |
2 |
|
T10 |
1 |
|
T5 |
1 |
| others[2] |
1029 |
1 |
|
T1 |
1 |
|
T4 |
3 |
|
T111 |
1 |
| others[3] |
1694 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T40 |
5 |
| false |
522 |
1 |
|
T106 |
6 |
|
T291 |
8 |
|
T126 |
6 |
| true |
1394 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T106 |
8 |
|
T43 |
1 |
|
T102 |
1 |
| others[1] |
226 |
1 |
|
T106 |
13 |
|
T391 |
1 |
|
T222 |
1 |
| others[2] |
211 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T106 |
4 |
| others[3] |
351 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T31 |
1 |
| false |
119 |
1 |
|
T106 |
6 |
|
T137 |
1 |
|
T82 |
6 |
| true |
5580 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T106 |
6 |
|
T222 |
1 |
|
T102 |
1 |
| others[1] |
211 |
1 |
|
T106 |
13 |
|
T35 |
1 |
|
T392 |
1 |
| others[2] |
195 |
1 |
|
T53 |
1 |
|
T106 |
15 |
|
T307 |
1 |
| others[3] |
325 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T106 |
11 |
| false |
119 |
1 |
|
T106 |
7 |
|
T82 |
9 |
|
T83 |
4 |
| true |
5626 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T111 |
1 |
| others[1] |
1253 |
1 |
|
T4 |
1 |
|
T40 |
3 |
|
T106 |
26 |
| others[2] |
1205 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T40 |
1 |
| others[3] |
1978 |
1 |
|
T4 |
2 |
|
T10 |
1 |
|
T5 |
1 |
| false |
605 |
1 |
|
T4 |
1 |
|
T40 |
1 |
|
T106 |
10 |
| true |
434 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1190 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T56 |
1 |
| others[1] |
1205 |
1 |
|
T4 |
2 |
|
T40 |
3 |
|
T37 |
1 |
| others[2] |
1224 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T5 |
1 |
| others[3] |
2035 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T40 |
5 |
| false |
602 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T80 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
85 |
1 |
|
T5 |
1 |
|
T106 |
4 |
|
T43 |
1 |
| others[1] |
92 |
1 |
|
T6 |
1 |
|
T106 |
2 |
|
T388 |
1 |
| others[2] |
103 |
1 |
|
T18 |
1 |
|
T106 |
5 |
|
T41 |
1 |
| others[3] |
161 |
1 |
|
T17 |
1 |
|
T106 |
7 |
|
T222 |
1 |
| false |
61 |
1 |
|
T17 |
1 |
|
T106 |
4 |
|
T82 |
1 |
| true |
6182 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T106 |
8 |
| others[1] |
237 |
1 |
|
T15 |
1 |
|
T53 |
1 |
|
T106 |
12 |
| others[2] |
217 |
1 |
|
T106 |
7 |
|
T34 |
1 |
|
T389 |
1 |
| others[3] |
369 |
1 |
|
T106 |
11 |
|
T224 |
1 |
|
T392 |
1 |
| false |
110 |
1 |
|
T17 |
1 |
|
T106 |
10 |
|
T204 |
1 |
| true |
5533 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T4 |
3 |
|
T56 |
1 |
|
T40 |
1 |
| others[1] |
1033 |
1 |
|
T4 |
5 |
|
T15 |
1 |
|
T10 |
1 |
| others[2] |
1032 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
2 |
| others[3] |
1672 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| false |
545 |
1 |
|
T4 |
1 |
|
T40 |
4 |
|
T37 |
1 |
| true |
1368 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T106 |
10 |
|
T204 |
1 |
|
T209 |
1 |
| others[1] |
236 |
1 |
|
T106 |
9 |
|
T43 |
1 |
|
T224 |
1 |
| others[2] |
204 |
1 |
|
T106 |
11 |
|
T21 |
1 |
|
T25 |
1 |
| others[3] |
368 |
1 |
|
T15 |
1 |
|
T17 |
2 |
|
T6 |
1 |
| false |
101 |
1 |
|
T106 |
4 |
|
T62 |
1 |
|
T108 |
1 |
| true |
5568 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
183 |
1 |
|
T2 |
1 |
|
T106 |
11 |
|
T394 |
1 |
| others[1] |
225 |
1 |
|
T106 |
12 |
|
T43 |
1 |
|
T222 |
1 |
| others[2] |
212 |
1 |
|
T17 |
1 |
|
T106 |
6 |
|
T35 |
1 |
| others[3] |
334 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T6 |
1 |
| false |
100 |
1 |
|
T53 |
1 |
|
T106 |
7 |
|
T82 |
8 |
| true |
5630 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T4 |
2 |
|
T40 |
3 |
|
T12 |
1 |
| others[1] |
1214 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
2 |
| others[2] |
1205 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T56 |
1 |
| others[3] |
2008 |
1 |
|
T4 |
6 |
|
T17 |
1 |
|
T111 |
1 |
| false |
578 |
1 |
|
T5 |
1 |
|
T40 |
1 |
|
T106 |
9 |
| true |
442 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T56 |
1 |
| others[1] |
1192 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T176 |
1 |
| others[2] |
1206 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| others[3] |
2022 |
1 |
|
T4 |
6 |
|
T111 |
1 |
|
T40 |
1 |
| false |
628 |
1 |
|
T3 |
1 |
|
T40 |
3 |
|
T106 |
12 |
| true |
421 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T222 |
1 |
| others[1] |
105 |
1 |
|
T106 |
4 |
|
T222 |
1 |
|
T389 |
1 |
| others[2] |
104 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T106 |
2 |
| others[3] |
164 |
1 |
|
T106 |
1 |
|
T43 |
1 |
|
T388 |
1 |
| false |
48 |
1 |
|
T106 |
2 |
|
T82 |
1 |
|
T98 |
1 |
| true |
6160 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
187 |
1 |
|
T18 |
1 |
|
T106 |
9 |
|
T388 |
1 |
| others[1] |
212 |
1 |
|
T106 |
6 |
|
T43 |
1 |
|
T82 |
9 |
| others[2] |
244 |
1 |
|
T6 |
1 |
|
T53 |
1 |
|
T106 |
15 |
| others[3] |
405 |
1 |
|
T3 |
1 |
|
T106 |
18 |
|
T391 |
1 |
| false |
116 |
1 |
|
T106 |
5 |
|
T21 |
1 |
|
T389 |
1 |
| true |
5520 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T4 |
5 |
|
T10 |
1 |
|
T40 |
4 |
| others[1] |
991 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T40 |
2 |
| others[2] |
1007 |
1 |
|
T1 |
1 |
|
T56 |
1 |
|
T40 |
3 |
| others[3] |
1676 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T17 |
1 |
| false |
542 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T40 |
1 |
| true |
1390 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T53 |
1 |
|
T106 |
8 |
|
T209 |
1 |
| others[1] |
214 |
1 |
|
T20 |
1 |
|
T106 |
10 |
|
T21 |
1 |
| others[2] |
214 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T19 |
1 |
| others[3] |
355 |
1 |
|
T17 |
1 |
|
T106 |
22 |
|
T34 |
1 |
| false |
116 |
1 |
|
T106 |
5 |
|
T35 |
1 |
|
T393 |
1 |
| true |
5578 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T6 |
1 |
|
T106 |
10 |
|
T307 |
1 |
| others[1] |
178 |
1 |
|
T106 |
5 |
|
T43 |
1 |
|
T82 |
15 |
| others[2] |
195 |
1 |
|
T106 |
13 |
|
T392 |
1 |
|
T82 |
10 |
| others[3] |
376 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T106 |
12 |
| false |
106 |
1 |
|
T106 |
6 |
|
T388 |
1 |
|
T82 |
6 |
| true |
5609 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |