Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T40 |
2 |
| others[1] |
1126 |
1 |
|
T4 |
4 |
|
T40 |
1 |
|
T106 |
15 |
| others[2] |
1193 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| others[3] |
2034 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T17 |
1 |
| false |
650 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T37 |
3 |
| true |
438 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T4 |
3 |
|
T40 |
4 |
|
T176 |
1 |
| others[1] |
1199 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T17 |
1 |
| others[2] |
1226 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T111 |
1 |
| others[3] |
2008 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| false |
596 |
1 |
|
T106 |
11 |
|
T235 |
1 |
|
T291 |
7 |
| true |
416 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T17 |
1 |
|
T106 |
1 |
|
T389 |
1 |
| others[1] |
111 |
1 |
|
T2 |
1 |
|
T106 |
3 |
|
T392 |
1 |
| others[2] |
97 |
1 |
|
T106 |
6 |
|
T222 |
1 |
|
T204 |
1 |
| others[3] |
153 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T106 |
5 |
| false |
46 |
1 |
|
T17 |
1 |
|
T106 |
2 |
|
T388 |
1 |
| true |
6176 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T106 |
13 |
| others[1] |
228 |
1 |
|
T15 |
1 |
|
T106 |
12 |
|
T224 |
1 |
| others[2] |
190 |
1 |
|
T6 |
1 |
|
T53 |
1 |
|
T18 |
1 |
| others[3] |
356 |
1 |
|
T106 |
15 |
|
T21 |
1 |
|
T32 |
1 |
| false |
115 |
1 |
|
T106 |
9 |
|
T391 |
1 |
|
T82 |
7 |
| true |
5573 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T4 |
4 |
|
T40 |
1 |
|
T176 |
1 |
| others[1] |
1047 |
1 |
|
T17 |
1 |
|
T56 |
1 |
|
T40 |
1 |
| others[2] |
1031 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T111 |
1 |
| others[3] |
1670 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T17 |
1 |
| false |
497 |
1 |
|
T16 |
1 |
|
T40 |
3 |
|
T20 |
1 |
| true |
1421 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T53 |
1 |
|
T31 |
1 |
|
T106 |
13 |
| others[1] |
209 |
1 |
|
T106 |
6 |
|
T209 |
1 |
|
T392 |
1 |
| others[2] |
237 |
1 |
|
T19 |
1 |
|
T106 |
22 |
|
T21 |
1 |
| others[3] |
341 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| false |
118 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T106 |
1 |
| true |
5550 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T106 |
10 |
| others[1] |
182 |
1 |
|
T19 |
1 |
|
T106 |
10 |
|
T41 |
1 |
| others[2] |
205 |
1 |
|
T5 |
1 |
|
T106 |
15 |
|
T391 |
1 |
| others[3] |
332 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T106 |
16 |
| false |
91 |
1 |
|
T3 |
1 |
|
T106 |
2 |
|
T34 |
1 |
| true |
5674 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T4 |
3 |
|
T12 |
1 |
|
T176 |
1 |
| others[1] |
1221 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
1232 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
3 |
| others[3] |
1949 |
1 |
|
T4 |
5 |
|
T56 |
1 |
|
T40 |
2 |
| false |
644 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T37 |
1 |
| true |
443 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1166 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T111 |
1 |
| others[1] |
1151 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
3 |
| others[2] |
1207 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T5 |
1 |
| others[3] |
2085 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
4 |
| false |
653 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T106 |
16 |
| true |
422 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T5 |
1 |
|
T106 |
1 |
|
T34 |
1 |
| others[1] |
108 |
1 |
|
T17 |
1 |
|
T106 |
4 |
|
T392 |
1 |
| others[2] |
102 |
1 |
|
T106 |
2 |
|
T389 |
1 |
|
T82 |
4 |
| others[3] |
160 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T106 |
7 |
| false |
55 |
1 |
|
T31 |
1 |
|
T82 |
1 |
|
T98 |
1 |
| true |
6167 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T106 |
10 |
| others[1] |
215 |
1 |
|
T2 |
1 |
|
T106 |
19 |
|
T41 |
1 |
| others[2] |
203 |
1 |
|
T18 |
1 |
|
T106 |
7 |
|
T273 |
1 |
| others[3] |
374 |
1 |
|
T19 |
1 |
|
T106 |
23 |
|
T224 |
1 |
| false |
118 |
1 |
|
T3 |
1 |
|
T106 |
5 |
|
T388 |
1 |
| true |
5571 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T3 |
1 |
|
T56 |
1 |
|
T40 |
4 |
| others[1] |
978 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T16 |
1 |
| others[2] |
1030 |
1 |
|
T4 |
3 |
|
T40 |
2 |
|
T39 |
1 |
| others[3] |
1691 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T17 |
1 |
| false |
524 |
1 |
|
T17 |
1 |
|
T111 |
1 |
|
T37 |
1 |
| true |
1398 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T31 |
1 |
|
T106 |
8 |
|
T222 |
1 |
| others[1] |
223 |
1 |
|
T18 |
1 |
|
T20 |
1 |
|
T106 |
10 |
| others[2] |
189 |
1 |
|
T3 |
1 |
|
T106 |
5 |
|
T41 |
1 |
| others[3] |
357 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T106 |
15 |
| false |
119 |
1 |
|
T106 |
4 |
|
T388 |
1 |
|
T82 |
4 |
| true |
5579 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
195 |
1 |
|
T106 |
6 |
|
T391 |
1 |
|
T222 |
1 |
| others[1] |
198 |
1 |
|
T3 |
1 |
|
T106 |
11 |
|
T389 |
1 |
| others[2] |
201 |
1 |
|
T17 |
1 |
|
T106 |
11 |
|
T41 |
1 |
| others[3] |
369 |
1 |
|
T2 |
1 |
|
T106 |
20 |
|
T392 |
1 |
| false |
115 |
1 |
|
T5 |
1 |
|
T106 |
5 |
|
T388 |
1 |
| true |
5606 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T56 |
1 |
| others[1] |
1238 |
1 |
|
T4 |
2 |
|
T40 |
1 |
|
T106 |
21 |
| others[2] |
1207 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T176 |
1 |
| others[3] |
1971 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T17 |
1 |
| false |
646 |
1 |
|
T4 |
2 |
|
T111 |
1 |
|
T106 |
10 |
| true |
440 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1196 |
1 |
|
T4 |
1 |
|
T17 |
2 |
|
T5 |
1 |
| others[1] |
1206 |
1 |
|
T4 |
4 |
|
T40 |
6 |
|
T176 |
1 |
| others[2] |
1180 |
1 |
|
T4 |
2 |
|
T40 |
4 |
|
T219 |
1 |
| others[3] |
2035 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T10 |
1 |
| false |
651 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T40 |
1 |
| true |
416 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T17 |
2 |
|
T53 |
1 |
|
T106 |
6 |
| others[1] |
102 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T106 |
11 |
| others[2] |
95 |
1 |
|
T106 |
1 |
|
T222 |
1 |
|
T392 |
1 |
| others[3] |
155 |
1 |
|
T106 |
8 |
|
T82 |
5 |
|
T83 |
3 |
| false |
64 |
1 |
|
T106 |
1 |
|
T43 |
1 |
|
T392 |
1 |
| true |
6166 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T21 |
1 |
| others[1] |
211 |
1 |
|
T20 |
1 |
|
T106 |
11 |
|
T222 |
1 |
| others[2] |
241 |
1 |
|
T106 |
12 |
|
T394 |
1 |
|
T278 |
1 |
| others[3] |
374 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T106 |
24 |
| false |
125 |
1 |
|
T6 |
1 |
|
T106 |
9 |
|
T82 |
3 |
| true |
5519 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1048 |
1 |
|
T15 |
1 |
|
T40 |
4 |
|
T7 |
1 |
| others[1] |
1055 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T111 |
1 |
| others[2] |
1051 |
1 |
|
T1 |
1 |
|
T4 |
4 |
|
T10 |
1 |
| others[3] |
1706 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T40 |
3 |
| false |
477 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T40 |
3 |
| true |
1347 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T106 |
8 |
|
T43 |
1 |
|
T35 |
1 |
| others[1] |
199 |
1 |
|
T106 |
5 |
|
T392 |
1 |
|
T82 |
4 |
| others[2] |
194 |
1 |
|
T17 |
1 |
|
T106 |
12 |
|
T82 |
13 |
| others[3] |
393 |
1 |
|
T20 |
1 |
|
T106 |
20 |
|
T391 |
1 |
| false |
108 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T204 |
1 |
| true |
5592 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T106 |
12 |
| others[1] |
216 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T106 |
10 |
| others[2] |
183 |
1 |
|
T18 |
1 |
|
T106 |
8 |
|
T41 |
1 |
| others[3] |
343 |
1 |
|
T2 |
1 |
|
T106 |
15 |
|
T388 |
1 |
| false |
89 |
1 |
|
T6 |
1 |
|
T106 |
7 |
|
T224 |
1 |
| true |
5640 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T106 |
16 |
| others[1] |
1177 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| others[2] |
1231 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T111 |
1 |
| others[3] |
1994 |
1 |
|
T4 |
5 |
|
T10 |
1 |
|
T5 |
1 |
| false |
616 |
1 |
|
T4 |
2 |
|
T40 |
1 |
|
T106 |
12 |
| true |
439 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T56 |
1 |
|
T111 |
1 |
|
T40 |
5 |
| others[1] |
1204 |
1 |
|
T4 |
4 |
|
T40 |
6 |
|
T31 |
1 |
| others[2] |
1151 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
2 |
| others[3] |
2040 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T5 |
1 |
| false |
631 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T176 |
1 |
| true |
427 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T82 |
3 |
| others[1] |
103 |
1 |
|
T106 |
6 |
|
T43 |
1 |
|
T388 |
1 |
| others[2] |
103 |
1 |
|
T106 |
4 |
|
T392 |
1 |
|
T102 |
1 |
| others[3] |
152 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T222 |
2 |
| false |
54 |
1 |
|
T106 |
3 |
|
T82 |
3 |
|
T83 |
4 |
| true |
6160 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T17 |
1 |
|
T106 |
10 |
|
T107 |
1 |
| others[1] |
228 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T53 |
1 |
| others[2] |
204 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T106 |
4 |
| others[3] |
348 |
1 |
|
T31 |
1 |
|
T106 |
16 |
|
T390 |
1 |
| false |
110 |
1 |
|
T2 |
1 |
|
T106 |
4 |
|
T21 |
1 |
| true |
5591 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1077 |
1 |
|
T4 |
4 |
|
T111 |
1 |
|
T40 |
1 |
| others[1] |
1015 |
1 |
|
T1 |
1 |
|
T4 |
3 |
|
T17 |
1 |
| others[2] |
1004 |
1 |
|
T4 |
3 |
|
T56 |
1 |
|
T40 |
1 |
| others[3] |
1678 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| false |
544 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T40 |
2 |
| true |
1366 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T31 |
1 |
| others[1] |
218 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T106 |
9 |
| others[2] |
204 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T106 |
10 |
| others[3] |
339 |
1 |
|
T2 |
1 |
|
T106 |
13 |
|
T222 |
1 |
| false |
99 |
1 |
|
T53 |
1 |
|
T19 |
1 |
|
T106 |
5 |
| true |
5603 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T53 |
1 |
|
T31 |
1 |
|
T106 |
10 |
| others[1] |
208 |
1 |
|
T6 |
1 |
|
T18 |
1 |
|
T106 |
7 |
| others[2] |
208 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T106 |
12 |
| others[3] |
342 |
1 |
|
T17 |
1 |
|
T106 |
17 |
|
T224 |
1 |
| false |
111 |
1 |
|
T106 |
10 |
|
T389 |
1 |
|
T393 |
1 |
| true |
5606 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T40 |
2 |
| others[1] |
1214 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T40 |
5 |
| others[2] |
1165 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T37 |
2 |
| others[3] |
1989 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T56 |
1 |
| false |
665 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
1 |
| true |
436 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| others[1] |
1187 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T40 |
5 |
| others[2] |
1188 |
1 |
|
T4 |
4 |
|
T40 |
4 |
|
T106 |
21 |
| others[3] |
2022 |
1 |
|
T4 |
6 |
|
T56 |
1 |
|
T111 |
1 |
| false |
616 |
1 |
|
T40 |
1 |
|
T37 |
1 |
|
T106 |
8 |
| true |
412 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T17 |
1 |
|
T106 |
8 |
|
T222 |
1 |
| others[1] |
110 |
1 |
|
T2 |
1 |
|
T53 |
1 |
|
T31 |
1 |
| others[2] |
90 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T388 |
1 |
| others[3] |
158 |
1 |
|
T106 |
5 |
|
T389 |
1 |
|
T392 |
1 |
| false |
50 |
1 |
|
T106 |
2 |
|
T43 |
1 |
|
T196 |
1 |
| true |
6188 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |