Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T106 |
11 |
| others[1] |
228 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T106 |
10 |
| others[2] |
224 |
1 |
|
T106 |
8 |
|
T43 |
1 |
|
T62 |
1 |
| others[3] |
395 |
1 |
|
T20 |
1 |
|
T106 |
18 |
|
T222 |
1 |
| false |
122 |
1 |
|
T106 |
2 |
|
T222 |
1 |
|
T394 |
1 |
| true |
5504 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1086 |
1 |
|
T1 |
1 |
|
T4 |
3 |
|
T17 |
2 |
| others[1] |
991 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T40 |
5 |
| others[2] |
975 |
1 |
|
T4 |
2 |
|
T40 |
4 |
|
T105 |
1 |
| others[3] |
1713 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T111 |
1 |
| false |
497 |
1 |
|
T4 |
2 |
|
T219 |
1 |
|
T106 |
9 |
| true |
1422 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T17 |
1 |
|
T6 |
1 |
|
T106 |
7 |
| others[1] |
209 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| others[2] |
208 |
1 |
|
T31 |
1 |
|
T106 |
17 |
|
T390 |
1 |
| others[3] |
360 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T20 |
1 |
| false |
105 |
1 |
|
T106 |
3 |
|
T392 |
1 |
|
T278 |
1 |
| true |
5588 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
194 |
1 |
|
T106 |
8 |
|
T389 |
1 |
|
T137 |
1 |
| others[1] |
184 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T106 |
13 |
| others[2] |
182 |
1 |
|
T106 |
14 |
|
T43 |
1 |
|
T82 |
7 |
| others[3] |
359 |
1 |
|
T53 |
1 |
|
T18 |
1 |
|
T106 |
14 |
| false |
121 |
1 |
|
T106 |
2 |
|
T34 |
1 |
|
T82 |
1 |
| true |
5644 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1194 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T111 |
1 |
| others[1] |
1233 |
1 |
|
T4 |
4 |
|
T17 |
2 |
|
T5 |
1 |
| others[2] |
1229 |
1 |
|
T4 |
1 |
|
T40 |
4 |
|
T37 |
3 |
| others[3] |
1923 |
1 |
|
T4 |
3 |
|
T40 |
1 |
|
T176 |
1 |
| false |
664 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T40 |
1 |
| true |
441 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
2 |
| others[1] |
1223 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
1168 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T40 |
4 |
| others[3] |
1979 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T56 |
1 |
| false |
628 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T31 |
1 |
| true |
424 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T2 |
1 |
|
T106 |
7 |
|
T137 |
1 |
| others[1] |
87 |
1 |
|
T106 |
3 |
|
T392 |
1 |
|
T82 |
1 |
| others[2] |
103 |
1 |
|
T17 |
2 |
|
T106 |
6 |
|
T388 |
1 |
| others[3] |
167 |
1 |
|
T5 |
1 |
|
T106 |
3 |
|
T43 |
1 |
| false |
55 |
1 |
|
T106 |
1 |
|
T82 |
1 |
|
T83 |
1 |
| true |
6155 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T53 |
1 |
|
T106 |
12 |
|
T82 |
9 |
| others[1] |
220 |
1 |
|
T5 |
1 |
|
T31 |
1 |
|
T106 |
8 |
| others[2] |
227 |
1 |
|
T6 |
1 |
|
T106 |
9 |
|
T388 |
1 |
| others[3] |
356 |
1 |
|
T15 |
1 |
|
T20 |
1 |
|
T106 |
20 |
| false |
115 |
1 |
|
T3 |
1 |
|
T106 |
4 |
|
T392 |
1 |
| true |
5551 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T16 |
1 |
|
T5 |
1 |
|
T40 |
5 |
| others[1] |
977 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T40 |
3 |
| others[2] |
1043 |
1 |
|
T4 |
4 |
|
T40 |
5 |
|
T37 |
3 |
| others[3] |
1676 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T17 |
2 |
| false |
551 |
1 |
|
T4 |
2 |
|
T10 |
1 |
|
T40 |
1 |
| true |
1386 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T17 |
1 |
|
T106 |
7 |
|
T278 |
1 |
| others[1] |
222 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T18 |
1 |
| others[2] |
191 |
1 |
|
T106 |
9 |
|
T35 |
1 |
|
T389 |
1 |
| others[3] |
352 |
1 |
|
T2 |
1 |
|
T53 |
1 |
|
T20 |
1 |
| false |
103 |
1 |
|
T106 |
2 |
|
T41 |
1 |
|
T82 |
4 |
| true |
5620 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T2 |
1 |
|
T106 |
6 |
|
T43 |
1 |
| others[1] |
212 |
1 |
|
T17 |
1 |
|
T6 |
1 |
|
T106 |
9 |
| others[2] |
228 |
1 |
|
T106 |
18 |
|
T391 |
1 |
|
T137 |
1 |
| others[3] |
334 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T106 |
17 |
| false |
110 |
1 |
|
T53 |
1 |
|
T106 |
4 |
|
T388 |
1 |
| true |
5601 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1173 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T111 |
1 |
| others[1] |
1183 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T40 |
2 |
| others[2] |
1215 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| others[3] |
2043 |
1 |
|
T4 |
3 |
|
T40 |
2 |
|
T176 |
1 |
| false |
631 |
1 |
|
T4 |
1 |
|
T106 |
14 |
|
T43 |
1 |
| true |
439 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T4 |
3 |
|
T111 |
1 |
|
T40 |
3 |
| others[1] |
1205 |
1 |
|
T4 |
2 |
|
T40 |
6 |
|
T37 |
2 |
| others[2] |
1201 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T40 |
1 |
| others[3] |
2018 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T56 |
1 |
| false |
652 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T106 |
4 |
|
T222 |
1 |
|
T82 |
2 |
| others[1] |
105 |
1 |
|
T2 |
1 |
|
T17 |
2 |
|
T106 |
2 |
| others[2] |
109 |
1 |
|
T5 |
1 |
|
T106 |
9 |
|
T43 |
1 |
| others[3] |
152 |
1 |
|
T106 |
7 |
|
T388 |
1 |
|
T222 |
1 |
| false |
49 |
1 |
|
T106 |
1 |
|
T82 |
3 |
|
T83 |
3 |
| true |
6175 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T106 |
8 |
| others[1] |
216 |
1 |
|
T31 |
1 |
|
T106 |
15 |
|
T32 |
1 |
| others[2] |
224 |
1 |
|
T20 |
1 |
|
T106 |
9 |
|
T222 |
1 |
| others[3] |
371 |
1 |
|
T2 |
1 |
|
T53 |
1 |
|
T106 |
10 |
| false |
89 |
1 |
|
T17 |
1 |
|
T106 |
7 |
|
T62 |
1 |
| true |
5577 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1004 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T176 |
1 |
| others[1] |
1054 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T40 |
1 |
| others[2] |
996 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T40 |
3 |
| others[3] |
1719 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T17 |
2 |
| false |
497 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T19 |
1 |
| true |
1414 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
195 |
1 |
|
T18 |
1 |
|
T106 |
11 |
|
T21 |
1 |
| others[1] |
214 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T106 |
8 |
| others[2] |
200 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T53 |
1 |
| others[3] |
351 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T106 |
15 |
| false |
112 |
1 |
|
T106 |
5 |
|
T41 |
1 |
|
T82 |
4 |
| true |
5612 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
186 |
1 |
|
T106 |
9 |
|
T43 |
1 |
|
T82 |
8 |
| others[1] |
208 |
1 |
|
T19 |
1 |
|
T106 |
9 |
|
T388 |
1 |
| others[2] |
238 |
1 |
|
T106 |
12 |
|
T41 |
1 |
|
T82 |
14 |
| others[3] |
305 |
1 |
|
T3 |
1 |
|
T106 |
17 |
|
T137 |
1 |
| false |
113 |
1 |
|
T5 |
1 |
|
T106 |
2 |
|
T82 |
9 |
| true |
5634 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1202 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T106 |
17 |
| others[1] |
1231 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| others[2] |
1234 |
1 |
|
T4 |
4 |
|
T56 |
1 |
|
T40 |
3 |
| others[3] |
1928 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T40 |
5 |
| false |
655 |
1 |
|
T3 |
1 |
|
T111 |
1 |
|
T40 |
2 |
| true |
434 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T56 |
1 |
| others[1] |
1225 |
1 |
|
T4 |
2 |
|
T111 |
1 |
|
T40 |
4 |
| others[2] |
1186 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| others[3] |
2012 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T40 |
2 |
| false |
651 |
1 |
|
T4 |
1 |
|
T40 |
5 |
|
T37 |
2 |
| true |
421 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T106 |
4 |
|
T41 |
1 |
|
T222 |
1 |
| others[1] |
107 |
1 |
|
T17 |
1 |
|
T106 |
6 |
|
T222 |
1 |
| others[2] |
103 |
1 |
|
T106 |
1 |
|
T388 |
1 |
|
T394 |
1 |
| others[3] |
160 |
1 |
|
T17 |
1 |
|
T106 |
3 |
|
T43 |
1 |
| false |
37 |
1 |
|
T106 |
2 |
|
T83 |
1 |
|
T112 |
1 |
| true |
6180 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T2 |
1 |
|
T106 |
10 |
|
T391 |
1 |
| others[1] |
200 |
1 |
|
T17 |
1 |
|
T106 |
9 |
|
T204 |
1 |
| others[2] |
237 |
1 |
|
T19 |
1 |
|
T106 |
12 |
|
T62 |
1 |
| others[3] |
383 |
1 |
|
T15 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| false |
110 |
1 |
|
T106 |
3 |
|
T32 |
1 |
|
T107 |
1 |
| true |
5535 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T17 |
1 |
|
T56 |
1 |
|
T40 |
4 |
| others[1] |
1079 |
1 |
|
T4 |
3 |
|
T40 |
1 |
|
T53 |
1 |
| others[2] |
1039 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T5 |
1 |
| others[3] |
1717 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T17 |
1 |
| false |
494 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T40 |
1 |
| true |
1339 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T106 |
7 |
|
T43 |
1 |
|
T388 |
1 |
| others[1] |
230 |
1 |
|
T53 |
1 |
|
T106 |
13 |
|
T389 |
1 |
| others[2] |
189 |
1 |
|
T17 |
1 |
|
T106 |
11 |
|
T82 |
13 |
| others[3] |
355 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| false |
115 |
1 |
|
T106 |
7 |
|
T82 |
4 |
|
T94 |
1 |
| true |
5575 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T6 |
1 |
|
T106 |
6 |
|
T222 |
1 |
| others[1] |
207 |
1 |
|
T106 |
12 |
|
T391 |
1 |
|
T34 |
1 |
| others[2] |
190 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T19 |
1 |
| others[3] |
325 |
1 |
|
T2 |
1 |
|
T106 |
17 |
|
T389 |
1 |
| false |
113 |
1 |
|
T106 |
11 |
|
T224 |
1 |
|
T82 |
3 |
| true |
5644 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
3 |
| others[1] |
1192 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T176 |
1 |
| others[2] |
1244 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T7 |
1 |
| others[3] |
1995 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T111 |
1 |
| false |
593 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T106 |
11 |
| true |
444 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1180 |
1 |
|
T4 |
1 |
|
T40 |
3 |
|
T176 |
1 |
| others[1] |
1270 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
1174 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T40 |
5 |
| others[3] |
2027 |
1 |
|
T4 |
4 |
|
T111 |
1 |
|
T40 |
5 |
| false |
620 |
1 |
|
T56 |
1 |
|
T219 |
1 |
|
T106 |
14 |
| true |
413 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T17 |
2 |
|
T106 |
4 |
|
T389 |
1 |
| others[1] |
93 |
1 |
|
T19 |
1 |
|
T106 |
3 |
|
T43 |
1 |
| others[2] |
99 |
1 |
|
T2 |
1 |
|
T106 |
6 |
|
T222 |
1 |
| others[3] |
176 |
1 |
|
T31 |
1 |
|
T106 |
9 |
|
T222 |
1 |
| false |
54 |
1 |
|
T106 |
3 |
|
T388 |
1 |
|
T95 |
1 |
| true |
6169 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T53 |
1 |
| others[1] |
198 |
1 |
|
T106 |
7 |
|
T43 |
1 |
|
T388 |
1 |
| others[2] |
230 |
1 |
|
T17 |
1 |
|
T106 |
8 |
|
T82 |
12 |
| others[3] |
348 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T106 |
19 |
| false |
131 |
1 |
|
T106 |
6 |
|
T121 |
1 |
|
T137 |
1 |
| true |
5559 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
978 |
1 |
|
T111 |
1 |
|
T40 |
5 |
|
T12 |
1 |
| others[1] |
1025 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
4 |
| others[2] |
1039 |
1 |
|
T4 |
6 |
|
T15 |
1 |
|
T56 |
1 |
| others[3] |
1732 |
1 |
|
T1 |
1 |
|
T4 |
3 |
|
T17 |
1 |
| false |
528 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T40 |
1 |
| true |
1382 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| others[1] |
214 |
1 |
|
T15 |
1 |
|
T106 |
11 |
|
T82 |
9 |
| others[2] |
219 |
1 |
|
T17 |
1 |
|
T106 |
8 |
|
T41 |
1 |
| others[3] |
346 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T31 |
1 |
| false |
109 |
1 |
|
T106 |
6 |
|
T393 |
1 |
|
T278 |
1 |
| true |
5582 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |