Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T106 |
11 |
| others[1] |
220 |
1 |
|
T106 |
15 |
|
T204 |
1 |
|
T392 |
1 |
| others[2] |
201 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T31 |
1 |
| others[3] |
357 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T106 |
14 |
| false |
97 |
1 |
|
T19 |
1 |
|
T106 |
2 |
|
T41 |
1 |
| true |
5595 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| others[1] |
1218 |
1 |
|
T4 |
5 |
|
T10 |
1 |
|
T37 |
2 |
| others[2] |
1180 |
1 |
|
T4 |
2 |
|
T176 |
1 |
|
T31 |
1 |
| others[3] |
1998 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| false |
660 |
1 |
|
T40 |
3 |
|
T106 |
8 |
|
T291 |
9 |
| true |
429 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1148 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T40 |
2 |
| others[1] |
1178 |
1 |
|
T4 |
3 |
|
T17 |
2 |
|
T56 |
1 |
| others[2] |
1222 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T40 |
3 |
| others[3] |
2058 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T40 |
6 |
| false |
657 |
1 |
|
T4 |
2 |
|
T40 |
1 |
|
T37 |
1 |
| true |
421 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T106 |
4 |
|
T222 |
2 |
|
T82 |
3 |
| others[1] |
99 |
1 |
|
T17 |
1 |
|
T106 |
6 |
|
T252 |
1 |
| others[2] |
107 |
1 |
|
T2 |
1 |
|
T106 |
6 |
|
T389 |
1 |
| others[3] |
176 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T388 |
1 |
| false |
56 |
1 |
|
T106 |
2 |
|
T43 |
1 |
|
T393 |
1 |
| true |
6146 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T106 |
8 |
| others[1] |
244 |
1 |
|
T106 |
12 |
|
T43 |
1 |
|
T62 |
1 |
| others[2] |
237 |
1 |
|
T106 |
13 |
|
T391 |
1 |
|
T209 |
1 |
| others[3] |
358 |
1 |
|
T5 |
1 |
|
T106 |
17 |
|
T35 |
1 |
| false |
111 |
1 |
|
T31 |
1 |
|
T106 |
3 |
|
T224 |
1 |
| true |
5522 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1033 |
1 |
|
T40 |
3 |
|
T18 |
1 |
|
T176 |
1 |
| others[1] |
1020 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T105 |
1 |
| others[2] |
1008 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T17 |
2 |
| others[3] |
1715 |
1 |
|
T4 |
2 |
|
T111 |
1 |
|
T40 |
6 |
| false |
503 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T40 |
2 |
| true |
1405 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T106 |
10 |
|
T224 |
1 |
|
T41 |
1 |
| others[1] |
217 |
1 |
|
T15 |
1 |
|
T106 |
13 |
|
T43 |
1 |
| others[2] |
207 |
1 |
|
T31 |
1 |
|
T19 |
1 |
|
T106 |
10 |
| others[3] |
307 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T20 |
1 |
| false |
120 |
1 |
|
T106 |
2 |
|
T34 |
1 |
|
T394 |
1 |
| true |
5607 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
178 |
1 |
|
T106 |
8 |
|
T389 |
1 |
|
T307 |
1 |
| others[1] |
212 |
1 |
|
T106 |
11 |
|
T388 |
1 |
|
T82 |
6 |
| others[2] |
211 |
1 |
|
T17 |
1 |
|
T106 |
7 |
|
T41 |
1 |
| others[3] |
365 |
1 |
|
T3 |
1 |
|
T106 |
8 |
|
T224 |
1 |
| false |
132 |
1 |
|
T106 |
3 |
|
T43 |
1 |
|
T392 |
1 |
| true |
5586 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T37 |
2 |
| others[1] |
1222 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T56 |
1 |
| others[2] |
1209 |
1 |
|
T4 |
3 |
|
T40 |
1 |
|
T160 |
1 |
| others[3] |
1936 |
1 |
|
T4 |
3 |
|
T111 |
1 |
|
T40 |
3 |
| false |
639 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| true |
440 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T4 |
3 |
|
T111 |
1 |
|
T40 |
5 |
| others[1] |
1189 |
1 |
|
T4 |
3 |
|
T40 |
3 |
|
T176 |
1 |
| others[2] |
1181 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T17 |
1 |
| others[3] |
2073 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| false |
602 |
1 |
|
T4 |
1 |
|
T40 |
1 |
|
T37 |
3 |
| true |
413 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T31 |
1 |
|
T106 |
4 |
|
T43 |
1 |
| others[1] |
101 |
1 |
|
T106 |
2 |
|
T392 |
2 |
|
T83 |
5 |
| others[2] |
107 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T106 |
5 |
| others[3] |
162 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T106 |
5 |
| false |
49 |
1 |
|
T106 |
4 |
|
T83 |
5 |
|
T395 |
1 |
| true |
6156 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T18 |
1 |
| others[1] |
219 |
1 |
|
T53 |
1 |
|
T31 |
1 |
|
T106 |
14 |
| others[2] |
222 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T106 |
8 |
| others[3] |
371 |
1 |
|
T106 |
14 |
|
T391 |
1 |
|
T62 |
1 |
| false |
115 |
1 |
|
T106 |
6 |
|
T102 |
1 |
|
T278 |
1 |
| true |
5540 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1028 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T17 |
1 |
| others[1] |
1027 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
1031 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T40 |
3 |
| others[3] |
1706 |
1 |
|
T4 |
3 |
|
T56 |
1 |
|
T111 |
1 |
| false |
522 |
1 |
|
T4 |
1 |
|
T176 |
1 |
|
T106 |
13 |
| true |
1370 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T106 |
5 |
|
T388 |
1 |
|
T137 |
1 |
| others[1] |
219 |
1 |
|
T106 |
8 |
|
T204 |
1 |
|
T82 |
10 |
| others[2] |
206 |
1 |
|
T106 |
8 |
|
T224 |
1 |
|
T391 |
1 |
| others[3] |
334 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T31 |
1 |
| false |
120 |
1 |
|
T5 |
1 |
|
T106 |
3 |
|
T34 |
1 |
| true |
5580 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
191 |
1 |
|
T31 |
1 |
|
T106 |
9 |
|
T35 |
1 |
| others[1] |
208 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T106 |
8 |
| others[2] |
209 |
1 |
|
T17 |
1 |
|
T6 |
1 |
|
T19 |
1 |
| others[3] |
338 |
1 |
|
T53 |
1 |
|
T106 |
19 |
|
T224 |
1 |
| false |
101 |
1 |
|
T3 |
1 |
|
T106 |
7 |
|
T41 |
1 |
| true |
5637 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T4 |
1 |
|
T40 |
3 |
|
T37 |
1 |
| others[1] |
1150 |
1 |
|
T4 |
5 |
|
T17 |
2 |
|
T56 |
1 |
| others[2] |
1209 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T40 |
1 |
| others[3] |
2070 |
1 |
|
T4 |
2 |
|
T111 |
1 |
|
T40 |
2 |
| false |
591 |
1 |
|
T40 |
1 |
|
T106 |
9 |
|
T291 |
6 |
| true |
444 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1187 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T40 |
2 |
| others[1] |
1259 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T56 |
1 |
| others[2] |
1158 |
1 |
|
T4 |
2 |
|
T40 |
3 |
|
T176 |
1 |
| others[3] |
2021 |
1 |
|
T4 |
5 |
|
T17 |
2 |
|
T40 |
3 |
| false |
636 |
1 |
|
T40 |
4 |
|
T106 |
12 |
|
T235 |
1 |
| true |
423 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T3 |
1 |
|
T106 |
5 |
|
T392 |
1 |
| others[1] |
104 |
1 |
|
T19 |
1 |
|
T106 |
5 |
|
T43 |
1 |
| others[2] |
100 |
1 |
|
T2 |
1 |
|
T106 |
6 |
|
T222 |
1 |
| others[3] |
170 |
1 |
|
T17 |
2 |
|
T106 |
4 |
|
T222 |
1 |
| false |
60 |
1 |
|
T5 |
1 |
|
T82 |
4 |
|
T98 |
1 |
| true |
6137 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T53 |
1 |
| others[1] |
195 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T106 |
6 |
| others[2] |
196 |
1 |
|
T106 |
9 |
|
T34 |
1 |
|
T273 |
1 |
| others[3] |
358 |
1 |
|
T106 |
20 |
|
T391 |
1 |
|
T62 |
1 |
| false |
122 |
1 |
|
T106 |
6 |
|
T388 |
1 |
|
T82 |
5 |
| true |
5588 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T4 |
4 |
|
T40 |
6 |
|
T53 |
1 |
| others[1] |
1015 |
1 |
|
T4 |
4 |
|
T16 |
1 |
|
T17 |
1 |
| others[2] |
1000 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T12 |
1 |
| others[3] |
1696 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| false |
513 |
1 |
|
T40 |
1 |
|
T176 |
1 |
|
T37 |
2 |
| true |
1404 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T106 |
8 |
| others[1] |
230 |
1 |
|
T19 |
1 |
|
T106 |
13 |
|
T391 |
1 |
| others[2] |
198 |
1 |
|
T6 |
1 |
|
T106 |
5 |
|
T43 |
1 |
| others[3] |
366 |
1 |
|
T2 |
1 |
|
T106 |
17 |
|
T32 |
1 |
| false |
122 |
1 |
|
T17 |
1 |
|
T106 |
6 |
|
T25 |
1 |
| true |
5563 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T53 |
1 |
|
T106 |
7 |
|
T391 |
1 |
| others[1] |
202 |
1 |
|
T106 |
10 |
|
T34 |
1 |
|
T389 |
1 |
| others[2] |
196 |
1 |
|
T5 |
1 |
|
T106 |
9 |
|
T41 |
1 |
| others[3] |
338 |
1 |
|
T2 |
1 |
|
T106 |
15 |
|
T224 |
1 |
| false |
99 |
1 |
|
T106 |
4 |
|
T388 |
1 |
|
T222 |
1 |
| true |
5647 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T40 |
1 |
|
T37 |
1 |
|
T106 |
14 |
| others[1] |
1246 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
1178 |
1 |
|
T4 |
5 |
|
T40 |
4 |
|
T176 |
1 |
| others[3] |
2007 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T56 |
1 |
| false |
595 |
1 |
|
T5 |
1 |
|
T40 |
1 |
|
T106 |
10 |
| true |
430 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1179 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T5 |
1 |
| others[1] |
1151 |
1 |
|
T4 |
1 |
|
T40 |
3 |
|
T106 |
15 |
| others[2] |
1247 |
1 |
|
T17 |
1 |
|
T56 |
1 |
|
T40 |
1 |
| others[3] |
2041 |
1 |
|
T4 |
4 |
|
T111 |
1 |
|
T40 |
5 |
| false |
641 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T106 |
9 |
| true |
425 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T106 |
2 |
|
T82 |
2 |
|
T98 |
1 |
| others[1] |
110 |
1 |
|
T106 |
2 |
|
T43 |
1 |
|
T204 |
1 |
| others[2] |
109 |
1 |
|
T17 |
1 |
|
T106 |
5 |
|
T388 |
1 |
| others[3] |
150 |
1 |
|
T17 |
1 |
|
T106 |
9 |
|
T41 |
1 |
| false |
39 |
1 |
|
T106 |
3 |
|
T82 |
1 |
|
T83 |
1 |
| true |
6171 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T31 |
1 |
|
T106 |
6 |
|
T82 |
12 |
| others[1] |
248 |
1 |
|
T17 |
2 |
|
T20 |
1 |
|
T106 |
12 |
| others[2] |
210 |
1 |
|
T106 |
14 |
|
T222 |
1 |
|
T209 |
1 |
| others[3] |
353 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| false |
110 |
1 |
|
T18 |
1 |
|
T106 |
5 |
|
T62 |
1 |
| true |
5536 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T4 |
1 |
|
T10 |
1 |
|
T37 |
1 |
| others[1] |
1043 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
2 |
| others[2] |
980 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T5 |
1 |
| others[3] |
1714 |
1 |
|
T4 |
3 |
|
T17 |
2 |
|
T56 |
1 |
| false |
524 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T12 |
1 |
| true |
1388 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T31 |
1 |
|
T106 |
7 |
|
T388 |
1 |
| others[1] |
229 |
1 |
|
T2 |
1 |
|
T106 |
6 |
|
T222 |
1 |
| others[2] |
215 |
1 |
|
T106 |
13 |
|
T43 |
1 |
|
T21 |
1 |
| others[3] |
370 |
1 |
|
T106 |
18 |
|
T391 |
1 |
|
T82 |
16 |
| false |
105 |
1 |
|
T106 |
2 |
|
T34 |
1 |
|
T82 |
4 |
| true |
5559 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T6 |
1 |
|
T106 |
17 |
|
T391 |
1 |
| others[1] |
183 |
1 |
|
T19 |
1 |
|
T106 |
13 |
|
T82 |
9 |
| others[2] |
197 |
1 |
|
T106 |
6 |
|
T222 |
1 |
|
T35 |
1 |
| others[3] |
331 |
1 |
|
T31 |
1 |
|
T106 |
22 |
|
T43 |
1 |
| false |
109 |
1 |
|
T106 |
3 |
|
T102 |
1 |
|
T393 |
1 |
| true |
5645 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T4 |
3 |
|
T17 |
2 |
|
T111 |
1 |
| others[1] |
1241 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T31 |
1 |
| others[2] |
1203 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T40 |
2 |
| others[3] |
1968 |
1 |
|
T4 |
3 |
|
T56 |
1 |
|
T40 |
4 |
| false |
639 |
1 |
|
T40 |
2 |
|
T219 |
1 |
|
T106 |
11 |
| true |
434 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11 |
1 |
|
T105 |
1 |
|
T76 |
1 |
|
T165 |
1 |
| others[1] |
5 |
1 |
|
T161 |
1 |
|
T133 |
1 |
|
T396 |
1 |
| others[2] |
6 |
1 |
|
T150 |
1 |
|
T397 |
1 |
|
T155 |
1 |
| others[3] |
16 |
1 |
|
T166 |
1 |
|
T77 |
1 |
|
T162 |
1 |
| false |
2 |
1 |
|
T398 |
1 |
|
T399 |
1 |
|
- |
- |
| true |
36 |
1 |
|
T149 |
2 |
|
T139 |
1 |
|
T143 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |