Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10767 |
1 |
|
T4 |
6 |
|
T11 |
2 |
|
T16 |
1 |
| others[1] |
779 |
1 |
|
T40 |
2 |
|
T55 |
1 |
|
T106 |
17 |
| others[2] |
765 |
1 |
|
T56 |
1 |
|
T40 |
4 |
|
T55 |
4 |
| others[3] |
1221 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T5 |
1 |
| false |
405 |
1 |
|
T111 |
1 |
|
T55 |
2 |
|
T31 |
1 |
| true |
521 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2462 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T56 |
1 |
| others[1] |
2479 |
1 |
|
T4 |
1 |
|
T17 |
2 |
|
T47 |
49 |
| others[2] |
2531 |
1 |
|
T4 |
4 |
|
T111 |
1 |
|
T47 |
43 |
| others[3] |
4117 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T6 |
1 |
| false |
1333 |
1 |
|
T4 |
2 |
|
T11 |
1 |
|
T47 |
29 |
| true |
1536 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10222 |
1 |
|
T11 |
2 |
|
T5 |
1 |
|
T47 |
199 |
| others[1] |
273 |
1 |
|
T17 |
1 |
|
T55 |
1 |
|
T106 |
14 |
| others[2] |
253 |
1 |
|
T31 |
1 |
|
T106 |
9 |
|
T100 |
1 |
| others[3] |
423 |
1 |
|
T18 |
1 |
|
T176 |
1 |
|
T20 |
1 |
| false |
138 |
1 |
|
T2 |
1 |
|
T53 |
1 |
|
T106 |
6 |
| true |
3149 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10477 |
1 |
|
T4 |
3 |
|
T11 |
2 |
|
T17 |
1 |
| others[1] |
457 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T111 |
1 |
| others[2] |
406 |
1 |
|
T40 |
1 |
|
T12 |
1 |
|
T140 |
1 |
| others[3] |
768 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
| false |
231 |
1 |
|
T39 |
1 |
|
T55 |
1 |
|
T106 |
5 |
| true |
2119 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10207 |
1 |
|
T15 |
1 |
|
T11 |
2 |
|
T47 |
199 |
| others[1] |
237 |
1 |
|
T18 |
1 |
|
T106 |
7 |
|
T235 |
1 |
| others[2] |
237 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T53 |
1 |
| others[3] |
408 |
1 |
|
T6 |
1 |
|
T31 |
1 |
|
T106 |
19 |
| false |
128 |
1 |
|
T106 |
6 |
|
T82 |
4 |
|
T83 |
9 |
| true |
3241 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10221 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
231 |
1 |
|
T31 |
1 |
|
T106 |
14 |
|
T34 |
1 |
| others[2] |
249 |
1 |
|
T111 |
1 |
|
T6 |
1 |
|
T176 |
1 |
| others[3] |
386 |
1 |
|
T56 |
1 |
|
T106 |
15 |
|
T204 |
1 |
| false |
116 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T106 |
7 |
| true |
3255 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10781 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T111 |
1 |
| others[1] |
782 |
1 |
|
T4 |
3 |
|
T40 |
4 |
|
T55 |
4 |
| others[2] |
705 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T40 |
2 |
| others[3] |
1251 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T40 |
4 |
| false |
416 |
1 |
|
T4 |
1 |
|
T55 |
1 |
|
T106 |
9 |
| true |
523 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10754 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T56 |
1 |
| others[1] |
756 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T40 |
3 |
| others[2] |
728 |
1 |
|
T4 |
3 |
|
T111 |
1 |
|
T40 |
1 |
| others[3] |
1262 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T40 |
1 |
| false |
398 |
1 |
|
T4 |
1 |
|
T40 |
4 |
|
T55 |
1 |
| true |
530 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2450 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T17 |
1 |
| others[1] |
2513 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
6 |
| others[2] |
2532 |
1 |
|
T47 |
40 |
|
T54 |
42 |
|
T42 |
34 |
| others[3] |
4206 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T56 |
1 |
| false |
1250 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T47 |
16 |
| true |
1477 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10234 |
1 |
|
T3 |
1 |
|
T11 |
2 |
|
T6 |
1 |
| others[1] |
272 |
1 |
|
T55 |
1 |
|
T106 |
10 |
|
T235 |
1 |
| others[2] |
227 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[3] |
419 |
1 |
|
T20 |
1 |
|
T55 |
2 |
|
T219 |
1 |
| false |
122 |
1 |
|
T106 |
5 |
|
T33 |
1 |
|
T389 |
1 |
| true |
3154 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10451 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T40 |
1 |
| others[1] |
421 |
1 |
|
T4 |
1 |
|
T40 |
3 |
|
T140 |
1 |
| others[2] |
424 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T10 |
1 |
| others[3] |
750 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T111 |
1 |
| false |
255 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T40 |
3 |
| true |
2127 |
1 |
|
T1 |
1 |
|
T4 |
5 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10242 |
1 |
|
T3 |
1 |
|
T11 |
2 |
|
T56 |
1 |
| others[1] |
230 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T106 |
7 |
| others[2] |
248 |
1 |
|
T5 |
1 |
|
T106 |
13 |
|
T62 |
1 |
| others[3] |
398 |
1 |
|
T17 |
2 |
|
T20 |
1 |
|
T31 |
1 |
| false |
125 |
1 |
|
T18 |
1 |
|
T176 |
1 |
|
T106 |
6 |
| true |
3185 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10198 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
244 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
230 |
1 |
|
T106 |
8 |
|
T224 |
1 |
|
T109 |
2 |
| others[3] |
426 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T106 |
20 |
| false |
118 |
1 |
|
T6 |
1 |
|
T106 |
5 |
|
T235 |
1 |
| true |
3212 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10736 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T11 |
2 |
| others[1] |
792 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T56 |
1 |
| others[2] |
754 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T55 |
4 |
| others[3] |
1242 |
1 |
|
T4 |
2 |
|
T10 |
1 |
|
T40 |
7 |
| false |
402 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T55 |
2 |
| true |
502 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10758 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T111 |
1 |
| others[1] |
765 |
1 |
|
T17 |
1 |
|
T55 |
2 |
|
T37 |
2 |
| others[2] |
751 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
2 |
| others[3] |
1218 |
1 |
|
T4 |
7 |
|
T56 |
1 |
|
T40 |
2 |
| false |
393 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T40 |
2 |
| true |
543 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2509 |
1 |
|
T4 |
3 |
|
T111 |
1 |
|
T47 |
38 |
| others[1] |
2485 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
| others[2] |
2385 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T47 |
37 |
| others[3] |
4284 |
1 |
|
T4 |
4 |
|
T11 |
1 |
|
T17 |
2 |
| false |
1288 |
1 |
|
T4 |
1 |
|
T47 |
11 |
|
T54 |
25 |
| true |
1477 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10237 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T18 |
1 |
| others[1] |
242 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T55 |
1 |
| others[2] |
255 |
1 |
|
T17 |
1 |
|
T111 |
1 |
|
T6 |
1 |
| others[3] |
405 |
1 |
|
T5 |
1 |
|
T55 |
2 |
|
T106 |
21 |
| false |
132 |
1 |
|
T3 |
1 |
|
T106 |
6 |
|
T121 |
1 |
| true |
3157 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10418 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
| others[1] |
436 |
1 |
|
T4 |
1 |
|
T40 |
1 |
|
T105 |
1 |
| others[2] |
453 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| others[3] |
721 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| false |
240 |
1 |
|
T4 |
2 |
|
T40 |
1 |
|
T12 |
1 |
| true |
2160 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10221 |
1 |
|
T3 |
1 |
|
T11 |
2 |
|
T17 |
1 |
| others[1] |
283 |
1 |
|
T2 |
1 |
|
T106 |
15 |
|
T235 |
1 |
| others[2] |
234 |
1 |
|
T106 |
7 |
|
T100 |
1 |
|
T32 |
1 |
| others[3] |
403 |
1 |
|
T106 |
18 |
|
T21 |
1 |
|
T391 |
1 |
| false |
119 |
1 |
|
T15 |
1 |
|
T20 |
1 |
|
T19 |
1 |
| true |
3168 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10225 |
1 |
|
T11 |
2 |
|
T5 |
1 |
|
T47 |
199 |
| others[1] |
230 |
1 |
|
T176 |
1 |
|
T106 |
12 |
|
T235 |
1 |
| others[2] |
208 |
1 |
|
T106 |
13 |
|
T101 |
1 |
|
T82 |
13 |
| others[3] |
398 |
1 |
|
T219 |
1 |
|
T106 |
19 |
|
T400 |
1 |
| false |
116 |
1 |
|
T19 |
1 |
|
T106 |
3 |
|
T196 |
1 |
| true |
3251 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10713 |
1 |
|
T4 |
2 |
|
T11 |
2 |
|
T56 |
1 |
| others[1] |
769 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
766 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T55 |
2 |
| others[3] |
1258 |
1 |
|
T4 |
3 |
|
T40 |
9 |
|
T55 |
3 |
| false |
405 |
1 |
|
T4 |
2 |
|
T40 |
1 |
|
T55 |
3 |
| true |
517 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10706 |
1 |
|
T4 |
2 |
|
T11 |
2 |
|
T17 |
1 |
| others[1] |
773 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T40 |
6 |
| others[2] |
793 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T56 |
1 |
| others[3] |
1239 |
1 |
|
T4 |
1 |
|
T40 |
6 |
|
T176 |
1 |
| false |
382 |
1 |
|
T4 |
2 |
|
T111 |
1 |
|
T55 |
1 |
| true |
535 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2507 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
4 |
| others[1] |
2497 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T47 |
33 |
| others[2] |
2575 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T111 |
1 |
| others[3] |
4125 |
1 |
|
T4 |
4 |
|
T11 |
1 |
|
T6 |
1 |
| false |
1240 |
1 |
|
T4 |
1 |
|
T47 |
31 |
|
T54 |
15 |
| true |
1484 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10257 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| others[1] |
260 |
1 |
|
T15 |
1 |
|
T55 |
2 |
|
T106 |
13 |
| others[2] |
283 |
1 |
|
T176 |
1 |
|
T219 |
1 |
|
T106 |
7 |
| others[3] |
396 |
1 |
|
T3 |
1 |
|
T56 |
1 |
|
T111 |
1 |
| false |
115 |
1 |
|
T31 |
1 |
|
T106 |
5 |
|
T224 |
1 |
| true |
3117 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10417 |
1 |
|
T1 |
1 |
|
T11 |
2 |
|
T40 |
3 |
| others[1] |
435 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
1 |
| others[2] |
463 |
1 |
|
T17 |
1 |
|
T40 |
1 |
|
T55 |
1 |
| others[3] |
740 |
1 |
|
T4 |
3 |
|
T40 |
6 |
|
T176 |
1 |
| false |
202 |
1 |
|
T4 |
1 |
|
T106 |
2 |
|
T291 |
5 |
| true |
2171 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10218 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
248 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T56 |
1 |
| others[2] |
248 |
1 |
|
T20 |
1 |
|
T106 |
9 |
|
T34 |
1 |
| others[3] |
387 |
1 |
|
T17 |
1 |
|
T176 |
1 |
|
T106 |
20 |
| false |
119 |
1 |
|
T53 |
1 |
|
T106 |
5 |
|
T21 |
1 |
| true |
3208 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10186 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
234 |
1 |
|
T111 |
1 |
|
T18 |
1 |
|
T106 |
5 |
| others[2] |
221 |
1 |
|
T5 |
1 |
|
T106 |
5 |
|
T81 |
1 |
| others[3] |
400 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T56 |
1 |
| false |
125 |
1 |
|
T106 |
5 |
|
T82 |
6 |
|
T83 |
5 |
| true |
3262 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10696 |
1 |
|
T4 |
3 |
|
T11 |
2 |
|
T111 |
1 |
| others[1] |
721 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T55 |
2 |
| others[2] |
784 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T40 |
2 |
| others[3] |
1298 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T40 |
6 |
| false |
414 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T40 |
2 |
| true |
515 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10754 |
1 |
|
T4 |
4 |
|
T11 |
2 |
|
T40 |
4 |
| others[1] |
744 |
1 |
|
T4 |
4 |
|
T56 |
1 |
|
T40 |
2 |
| others[2] |
751 |
1 |
|
T111 |
1 |
|
T40 |
5 |
|
T55 |
4 |
| others[3] |
1232 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| false |
424 |
1 |
|
T4 |
2 |
|
T40 |
1 |
|
T176 |
1 |
| true |
523 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2537 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T47 |
30 |
| others[1] |
2429 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T47 |
40 |
| others[2] |
2443 |
1 |
|
T4 |
3 |
|
T11 |
1 |
|
T111 |
1 |
| others[3] |
4244 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T56 |
1 |
| false |
1264 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T47 |
16 |
| true |
1511 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10256 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T47 |
199 |
| others[1] |
238 |
1 |
|
T53 |
1 |
|
T18 |
1 |
|
T55 |
1 |
| others[2] |
283 |
1 |
|
T15 |
1 |
|
T176 |
1 |
|
T19 |
1 |
| others[3] |
446 |
1 |
|
T5 |
1 |
|
T111 |
1 |
|
T55 |
2 |
| false |
120 |
1 |
|
T106 |
8 |
|
T82 |
7 |
|
T83 |
4 |
| true |
3085 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |