Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10436 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T5 |
1 |
| others[1] |
474 |
1 |
|
T17 |
1 |
|
T111 |
1 |
|
T40 |
1 |
| others[2] |
481 |
1 |
|
T4 |
3 |
|
T40 |
1 |
|
T6 |
1 |
| others[3] |
734 |
1 |
|
T1 |
1 |
|
T4 |
3 |
|
T16 |
1 |
| false |
226 |
1 |
|
T17 |
1 |
|
T106 |
3 |
|
T43 |
1 |
| true |
2077 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10221 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
222 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T106 |
15 |
| others[2] |
243 |
1 |
|
T3 |
1 |
|
T106 |
10 |
|
T235 |
1 |
| others[3] |
396 |
1 |
|
T17 |
1 |
|
T176 |
1 |
|
T20 |
1 |
| false |
139 |
1 |
|
T6 |
1 |
|
T106 |
3 |
|
T34 |
1 |
| true |
3207 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10194 |
1 |
|
T11 |
2 |
|
T111 |
1 |
|
T47 |
199 |
| others[1] |
213 |
1 |
|
T31 |
1 |
|
T106 |
13 |
|
T81 |
1 |
| others[2] |
224 |
1 |
|
T2 |
1 |
|
T106 |
9 |
|
T100 |
1 |
| others[3] |
413 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T106 |
18 |
| false |
120 |
1 |
|
T3 |
1 |
|
T106 |
7 |
|
T389 |
1 |
| true |
3264 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10731 |
1 |
|
T11 |
2 |
|
T5 |
1 |
|
T40 |
4 |
| others[1] |
781 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
4 |
| others[2] |
741 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T55 |
1 |
| others[3] |
1243 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T56 |
1 |
| false |
424 |
1 |
|
T4 |
3 |
|
T40 |
2 |
|
T55 |
1 |
| true |
508 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10650 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T40 |
2 |
| others[1] |
785 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T111 |
1 |
| others[2] |
746 |
1 |
|
T4 |
3 |
|
T40 |
3 |
|
T55 |
1 |
| others[3] |
1327 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T17 |
1 |
| false |
393 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
1 |
| true |
527 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2502 |
1 |
|
T4 |
1 |
|
T11 |
2 |
|
T17 |
1 |
| others[1] |
2495 |
1 |
|
T4 |
2 |
|
T47 |
30 |
|
T54 |
40 |
| others[2] |
2528 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T47 |
43 |
| others[3] |
4169 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T111 |
1 |
| false |
1290 |
1 |
|
T4 |
2 |
|
T47 |
22 |
|
T54 |
15 |
| true |
1444 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10258 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
293 |
1 |
|
T2 |
1 |
|
T55 |
1 |
|
T106 |
9 |
| others[2] |
224 |
1 |
|
T53 |
1 |
|
T18 |
1 |
|
T55 |
1 |
| others[3] |
461 |
1 |
|
T17 |
1 |
|
T56 |
1 |
|
T111 |
1 |
| false |
132 |
1 |
|
T5 |
1 |
|
T55 |
1 |
|
T106 |
3 |
| true |
3060 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10455 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T10 |
1 |
| others[1] |
474 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T55 |
1 |
| others[2] |
453 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T40 |
1 |
| others[3] |
708 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T40 |
1 |
| false |
228 |
1 |
|
T4 |
1 |
|
T111 |
1 |
|
T176 |
1 |
| true |
2110 |
1 |
|
T1 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10237 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T5 |
1 |
| others[1] |
247 |
1 |
|
T111 |
1 |
|
T176 |
1 |
|
T106 |
11 |
| others[2] |
246 |
1 |
|
T106 |
8 |
|
T391 |
1 |
|
T222 |
1 |
| others[3] |
415 |
1 |
|
T2 |
1 |
|
T106 |
26 |
|
T43 |
1 |
| false |
113 |
1 |
|
T106 |
3 |
|
T33 |
1 |
|
T393 |
1 |
| true |
3170 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10214 |
1 |
|
T3 |
1 |
|
T11 |
2 |
|
T56 |
1 |
| others[1] |
228 |
1 |
|
T219 |
1 |
|
T106 |
11 |
|
T100 |
1 |
| others[2] |
216 |
1 |
|
T6 |
1 |
|
T176 |
1 |
|
T106 |
10 |
| others[3] |
407 |
1 |
|
T106 |
23 |
|
T400 |
1 |
|
T41 |
1 |
| false |
114 |
1 |
|
T2 |
1 |
|
T53 |
1 |
|
T106 |
6 |
| true |
3249 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10722 |
1 |
|
T4 |
3 |
|
T11 |
2 |
|
T40 |
5 |
| others[1] |
730 |
1 |
|
T4 |
1 |
|
T10 |
1 |
|
T5 |
1 |
| others[2] |
752 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T40 |
2 |
| others[3] |
1319 |
1 |
|
T4 |
4 |
|
T111 |
1 |
|
T40 |
3 |
| false |
415 |
1 |
|
T56 |
1 |
|
T40 |
2 |
|
T55 |
3 |
| true |
490 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10738 |
1 |
|
T4 |
2 |
|
T11 |
2 |
|
T56 |
1 |
| others[1] |
765 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T40 |
4 |
| others[2] |
723 |
1 |
|
T111 |
1 |
|
T40 |
2 |
|
T55 |
2 |
| others[3] |
1284 |
1 |
|
T4 |
5 |
|
T40 |
3 |
|
T7 |
1 |
| false |
389 |
1 |
|
T4 |
3 |
|
T40 |
4 |
|
T176 |
1 |
| true |
529 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2544 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T11 |
1 |
| others[1] |
2565 |
1 |
|
T4 |
4 |
|
T17 |
1 |
|
T47 |
49 |
| others[2] |
2438 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
4161 |
1 |
|
T4 |
4 |
|
T111 |
1 |
|
T47 |
68 |
| false |
1287 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T47 |
21 |
| true |
1433 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10235 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
265 |
1 |
|
T2 |
1 |
|
T55 |
1 |
|
T219 |
1 |
| others[2] |
269 |
1 |
|
T55 |
4 |
|
T106 |
12 |
|
T36 |
1 |
| others[3] |
416 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T55 |
1 |
| false |
124 |
1 |
|
T106 |
3 |
|
T21 |
1 |
|
T22 |
1 |
| true |
3119 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10442 |
1 |
|
T4 |
2 |
|
T11 |
2 |
|
T17 |
2 |
| others[1] |
441 |
1 |
|
T40 |
4 |
|
T55 |
1 |
|
T31 |
1 |
| others[2] |
418 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T10 |
1 |
| others[3] |
767 |
1 |
|
T1 |
1 |
|
T4 |
4 |
|
T40 |
2 |
| false |
225 |
1 |
|
T4 |
1 |
|
T105 |
1 |
|
T55 |
2 |
| true |
2135 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10230 |
1 |
|
T11 |
2 |
|
T111 |
1 |
|
T47 |
199 |
| others[1] |
247 |
1 |
|
T56 |
1 |
|
T6 |
1 |
|
T106 |
5 |
| others[2] |
240 |
1 |
|
T31 |
1 |
|
T106 |
8 |
|
T81 |
1 |
| others[3] |
444 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T106 |
15 |
| false |
119 |
1 |
|
T176 |
1 |
|
T106 |
9 |
|
T41 |
1 |
| true |
3148 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10231 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
234 |
1 |
|
T53 |
1 |
|
T106 |
9 |
|
T224 |
1 |
| others[2] |
212 |
1 |
|
T2 |
1 |
|
T56 |
1 |
|
T106 |
11 |
| others[3] |
381 |
1 |
|
T17 |
2 |
|
T111 |
1 |
|
T31 |
1 |
| false |
138 |
1 |
|
T3 |
1 |
|
T106 |
4 |
|
T400 |
1 |
| true |
3232 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10759 |
1 |
|
T4 |
4 |
|
T11 |
2 |
|
T111 |
1 |
| others[1] |
751 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| others[2] |
746 |
1 |
|
T4 |
2 |
|
T56 |
1 |
|
T40 |
2 |
| others[3] |
1272 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T40 |
6 |
| false |
393 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T106 |
11 |
| true |
507 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10718 |
1 |
|
T4 |
2 |
|
T11 |
2 |
|
T56 |
1 |
| others[1] |
800 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T40 |
2 |
| others[2] |
778 |
1 |
|
T4 |
3 |
|
T40 |
3 |
|
T55 |
1 |
| others[3] |
1228 |
1 |
|
T4 |
1 |
|
T40 |
9 |
|
T55 |
5 |
| false |
374 |
1 |
|
T4 |
2 |
|
T176 |
1 |
|
T37 |
1 |
| true |
530 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2478 |
1 |
|
T4 |
3 |
|
T47 |
38 |
|
T54 |
35 |
| others[1] |
2423 |
1 |
|
T4 |
2 |
|
T47 |
33 |
|
T54 |
37 |
| others[2] |
2530 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T47 |
39 |
| others[3] |
4234 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T17 |
2 |
| false |
1310 |
1 |
|
T4 |
2 |
|
T11 |
1 |
|
T47 |
25 |
| true |
1453 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10266 |
1 |
|
T2 |
1 |
|
T11 |
2 |
|
T17 |
1 |
| others[1] |
263 |
1 |
|
T5 |
1 |
|
T55 |
2 |
|
T106 |
10 |
| others[2] |
243 |
1 |
|
T17 |
1 |
|
T55 |
1 |
|
T219 |
1 |
| others[3] |
432 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T31 |
1 |
| false |
140 |
1 |
|
T6 |
1 |
|
T106 |
3 |
|
T400 |
1 |
| true |
3084 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10435 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T11 |
2 |
| others[1] |
480 |
1 |
|
T111 |
1 |
|
T40 |
5 |
|
T39 |
1 |
| others[2] |
450 |
1 |
|
T40 |
1 |
|
T12 |
1 |
|
T7 |
1 |
| others[3] |
775 |
1 |
|
T4 |
4 |
|
T10 |
1 |
|
T17 |
1 |
| false |
203 |
1 |
|
T17 |
1 |
|
T56 |
1 |
|
T106 |
4 |
| true |
2085 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10229 |
1 |
|
T11 |
2 |
|
T47 |
199 |
|
T54 |
214 |
| others[1] |
243 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[2] |
256 |
1 |
|
T56 |
1 |
|
T18 |
1 |
|
T106 |
7 |
| others[3] |
378 |
1 |
|
T20 |
1 |
|
T31 |
1 |
|
T106 |
8 |
| false |
129 |
1 |
|
T5 |
1 |
|
T106 |
6 |
|
T235 |
1 |
| true |
3193 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10223 |
1 |
|
T11 |
2 |
|
T17 |
1 |
|
T47 |
199 |
| others[1] |
233 |
1 |
|
T106 |
10 |
|
T235 |
1 |
|
T222 |
1 |
| others[2] |
234 |
1 |
|
T6 |
1 |
|
T106 |
3 |
|
T224 |
1 |
| others[3] |
382 |
1 |
|
T219 |
1 |
|
T31 |
1 |
|
T106 |
18 |
| false |
110 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T18 |
1 |
| true |
3246 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10710 |
1 |
|
T11 |
2 |
|
T40 |
3 |
|
T47 |
199 |
| others[1] |
751 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T111 |
1 |
| others[2] |
777 |
1 |
|
T4 |
4 |
|
T56 |
1 |
|
T40 |
2 |
| others[3] |
1272 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T40 |
5 |
| false |
407 |
1 |
|
T4 |
2 |
|
T40 |
2 |
|
T106 |
9 |
| true |
511 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |