Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226124	1		T2	1366		T3	2		T4	8
auto[FlashEraseBank]	255299	1		T2	1175		T4	3		T15	17

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	267920	1		T2	1629		T4	6		T15	20
auto[FlashOpProgram]	193074	1		T2	912		T3	2		T4	2
auto[FlashOpErase]	16429	1		T4	3		T5	29		T40	30
auto[FlashOpInvalid]	4000	1		T117	200		T87	200		T289	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	267920	1		T2	1629		T4	6		T15	20
op[FlashOpProgram]	193074	1		T2	912		T3	2		T4	2
op[FlashOpErase]	16429	1		T4	3		T5	29		T40	30
read_erase_read	800	1		T4	1		T5	7		T31	7
read_prog_read	1400	1		T2	5		T4	1		T15	10

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	338582	1		T2	1786		T3	2		T4	11
auto[FlashPartInfo]	138937	1		T2	734		T15	28		T11	1
auto[FlashPartInfo1]	994	1		T2	8		T6	2		T19	2
auto[FlashPartInfo2]	2910	1		T2	13		T6	9		T20	2

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	202572	1		T2	1116		T4	6		T15	2
auto[FlashPartData]	auto[FlashOpProgram]	128573	1		T2	670		T3	2		T4	2
auto[FlashPartData]	auto[FlashOpErase]	3557	1		T4	3		T5	29		T40	30
auto[FlashPartData]	auto[FlashOpInvalid]	3880	1		T117	198		T87	190		T289	198
auto[FlashPartInfo]	auto[FlashOpRead]	62736	1		T2	497		T15	18		T11	1
auto[FlashPartInfo]	auto[FlashOpProgram]	63262	1		T2	237		T15	10		T5	2
auto[FlashPartInfo]	auto[FlashOpErase]	12839	1		T47	286		T105	1		T54	321
auto[FlashPartInfo]	auto[FlashOpInvalid]	100	1		T87	6		T289	2		T404	4
auto[FlashPartInfo1]	auto[FlashOpRead]	823	1		T2	8		T6	2		T19	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T113	1		T87	2		T405	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T87	2		T406	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T87	4		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1789	1		T2	8		T6	2		T20	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1075	1		T2	5		T6	7		T19	4
auto[FlashPartInfo2]	auto[FlashOpErase]	30	1		T117	1		T404	1		T407	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T117	2		T404	2		T408	2