Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32169	1		T4	1		T5	32		T40	12
auto[1]	19	1		T108	2		T173	2		T328	1
auto[2]	249	1		T40	4		T107	33		T209	30
auto[3]	252	1		T15	1		T20	1		T21	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8190	1		T15	1		T5	8		T40	4
evic_idx[1]	8182	1		T4	1		T5	8		T40	4
evic_idx[2]	8161	1		T5	8		T40	4		T47	141
evic_idx[3]	8156	1		T5	8		T40	4		T47	141

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31533	1		T47	564		T54	680		T42	492
evic_op[2]	532	1		T4	1		T15	1		T20	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7818	1		T47	141		T54	170		T42	123
evic_idx[0]	evic_op[1]	auto[2]	21	1		T209	12		T329	9		-	-
evic_idx[0]	evic_op[1]	auto[3]	63	1		T330	1		T331	39		T332	7
evic_idx[0]	evic_op[2]	auto[0]	82	1		T55	5		T106	2		T120	9
evic_idx[0]	evic_op[2]	auto[1]	7	1		T108	1		T333	2		T334	1
evic_idx[0]	evic_op[2]	auto[2]	32	1		T107	9		T335	7		T336	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T15	1		T36	1		T94	1
evic_idx[1]	evic_op[1]	auto[0]	7815	1		T47	141		T54	170		T42	123
evic_idx[1]	evic_op[1]	auto[2]	19	1		T209	9		T329	10		-	-
evic_idx[1]	evic_op[1]	auto[3]	53	1		T330	1		T331	33		T332	7
evic_idx[1]	evic_op[2]	auto[0]	77	1		T4	1		T55	5		T106	2
evic_idx[1]	evic_op[2]	auto[1]	4	1		T108	1		T337	1		T338	1
evic_idx[1]	evic_op[2]	auto[2]	46	1		T107	9		T335	8		T336	2
evic_idx[1]	evic_op[2]	auto[3]	12	1		T94	1		T308	1		T339	1
evic_idx[2]	evic_op[1]	auto[0]	7822	1		T47	141		T54	170		T42	123
evic_idx[2]	evic_op[1]	auto[2]	13	1		T209	7		T329	6		-	-
evic_idx[2]	evic_op[1]	auto[3]	45	1		T331	25		T332	8		T340	12
evic_idx[2]	evic_op[2]	auto[0]	77	1		T55	5		T106	2		T195	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T173	1		T341	1		T338	1
evic_idx[2]	evic_op[2]	auto[2]	33	1		T107	6		T110	2		T335	6
evic_idx[2]	evic_op[2]	auto[3]	12	1		T21	1		T342	1		T343	1
evic_idx[3]	evic_op[1]	auto[0]	7819	1		T47	141		T54	170		T42	123
evic_idx[3]	evic_op[1]	auto[2]	5	1		T209	2		T329	3		-	-
evic_idx[3]	evic_op[1]	auto[3]	40	1		T331	21		T332	7		T340	12
evic_idx[3]	evic_op[2]	auto[0]	79	1		T55	5		T106	2		T120	9
evic_idx[3]	evic_op[2]	auto[1]	5	1		T173	1		T328	1		T344	1
evic_idx[3]	evic_op[2]	auto[2]	36	1		T107	9		T335	3		T336	5
evic_idx[3]	evic_op[2]	auto[3]	17	1		T20	1		T277	1		T345	1