Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	34873	1		T313	9384		T325	8283		T326	2698
rd_lvl[2]	42146	1		T122	7672		T313	5192		T325	4245
rd_lvl[3]	15034	1		T32	714		T122	450		T190	770
rd_lvl[4]	22310	1		T32	1348		T122	1		T190	1178
rd_lvl[5]	19565	1		T32	95		T122	1		T278	1762
rd_lvl[6]	16838	1		T32	524		T129	1101		T122	1
rd_lvl[7]	12463	1		T32	661		T129	475		T273	999
rd_lvl[8]	10443	1		T32	139		T273	724		T278	59
rd_lvl[9]	6755	1		T32	1		T201	637		T190	1
rd_lvl[10]	5937	1		T32	1		T27	449		T327	551
rd_lvl[11]	7393	1		T27	246		T278	59		T327	243
rd_lvl[12]	8654	1		T33	547		T30	456		T122	1
rd_lvl[13]	7336	1		T32	119		T33	359		T25	345
rd_lvl[14]	4307	1		T25	851		T194	504		T326	16
rd_lvl[15]	3970	1		T30	2		T93	513		T192	306