Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	333968	1		T1	1		T2	2		T3	1
all_pins[1]	333968	1		T1	1		T2	2		T3	1
all_pins[2]	333968	1		T1	1		T2	2		T3	1
all_pins[3]	333968	1		T1	1		T2	2		T3	1
all_pins[4]	333968	1		T1	1		T2	2		T3	1
all_pins[5]	333968	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1679413	1		T1	6		T2	12		T3	6
values[0x1]	324395	1		T32	4519		T33	1812		T25	2392
transitions[0x0=>0x1]	300286	1		T32	3808		T33	1812		T25	2392
transitions[0x1=>0x0]	300280	1		T32	3808		T33	1812		T25	2392

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	333831	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	137	1		T259	2		T260	2		T261	2
all_pins[0]	transitions[0x0=>0x1]	75	1		T260	2		T261	2		T318	1
all_pins[0]	transitions[0x1=>0x0]	87	1		T259	2		T260	1		T261	2
all_pins[1]	values[0x0]	333819	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	149	1		T259	4		T260	1		T261	2
all_pins[1]	transitions[0x0=>0x1]	117	1		T259	3		T260	1		T261	1
all_pins[1]	transitions[0x1=>0x0]	1317	1		T93	222		T192	484		T350	286
all_pins[2]	values[0x0]	332619	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	1349	1		T93	222		T192	484		T350	286
all_pins[2]	transitions[0x0=>0x1]	50	1		T259	1		T260	2		T261	1
all_pins[2]	transitions[0x1=>0x0]	218551	1		T32	3602		T33	906		T25	1196
all_pins[3]	values[0x0]	114118	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	219850	1		T32	3602		T33	906		T25	1196
all_pins[3]	transitions[0x0=>0x1]	197200	1		T32	2891		T33	906		T25	1196
all_pins[3]	transitions[0x1=>0x0]	80186	1		T32	206		T33	906		T25	1196
all_pins[4]	values[0x0]	231132	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	102836	1		T32	917		T33	906		T25	1196
all_pins[4]	transitions[0x0=>0x1]	102815	1		T32	917		T33	906		T25	1196
all_pins[4]	transitions[0x1=>0x0]	53	1		T261	1		T319	1		T320	1
all_pins[5]	values[0x0]	333894	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	74	1		T261	1		T319	3		T320	4
all_pins[5]	transitions[0x0=>0x1]	29	1		T319	2		T320	2		T322	1
all_pins[5]	transitions[0x1=>0x0]	86	1		T259	1		T260	2		T261	1