| T1072 |
/workspace/coverage/default/11.flash_ctrl_mp_regions.3241077668 |
|
|
Apr 16 01:32:13 PM PDT 24 |
Apr 16 01:39:47 PM PDT 24 |
25046666800 ps |
| T1073 |
/workspace/coverage/default/7.flash_ctrl_disable.2090641607 |
|
|
Apr 16 01:30:07 PM PDT 24 |
Apr 16 01:30:28 PM PDT 24 |
27329200 ps |
| T1074 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1309199113 |
|
|
Apr 16 01:38:02 PM PDT 24 |
Apr 16 01:40:36 PM PDT 24 |
16860608300 ps |
| T1075 |
/workspace/coverage/default/28.flash_ctrl_prog_reset.3824120006 |
|
|
Apr 16 01:36:47 PM PDT 24 |
Apr 16 01:37:01 PM PDT 24 |
17770800 ps |
| T1076 |
/workspace/coverage/default/32.flash_ctrl_rw_evict.1621453783 |
|
|
Apr 16 01:37:17 PM PDT 24 |
Apr 16 01:37:50 PM PDT 24 |
56684800 ps |
| T1077 |
/workspace/coverage/default/39.flash_ctrl_intr_rd.3620402294 |
|
|
Apr 16 01:38:03 PM PDT 24 |
Apr 16 01:40:45 PM PDT 24 |
1262454500 ps |
| T1078 |
/workspace/coverage/default/34.flash_ctrl_otp_reset.1362835069 |
|
|
Apr 16 01:37:33 PM PDT 24 |
Apr 16 01:39:44 PM PDT 24 |
141158400 ps |
| T1079 |
/workspace/coverage/default/34.flash_ctrl_smoke.1178429008 |
|
|
Apr 16 01:37:31 PM PDT 24 |
Apr 16 01:40:47 PM PDT 24 |
329989700 ps |
| T1080 |
/workspace/coverage/default/63.flash_ctrl_connect.4066285862 |
|
|
Apr 16 01:38:59 PM PDT 24 |
Apr 16 01:39:15 PM PDT 24 |
65925700 ps |
| T1081 |
/workspace/coverage/default/57.flash_ctrl_connect.3734950803 |
|
|
Apr 16 01:38:57 PM PDT 24 |
Apr 16 01:39:14 PM PDT 24 |
37347000 ps |
| T159 |
/workspace/coverage/default/0.flash_ctrl_rma_err.1756846069 |
|
|
Apr 16 01:22:15 PM PDT 24 |
Apr 16 01:39:38 PM PDT 24 |
82137240300 ps |
| T1082 |
/workspace/coverage/default/53.flash_ctrl_otp_reset.3743445644 |
|
|
Apr 16 01:38:58 PM PDT 24 |
Apr 16 01:41:11 PM PDT 24 |
37357600 ps |
| T1083 |
/workspace/coverage/default/26.flash_ctrl_prog_reset.3551289589 |
|
|
Apr 16 01:36:26 PM PDT 24 |
Apr 16 01:36:45 PM PDT 24 |
75432000 ps |
| T1084 |
/workspace/coverage/default/4.flash_ctrl_wo.3677663475 |
|
|
Apr 16 01:27:10 PM PDT 24 |
Apr 16 01:30:19 PM PDT 24 |
12697056700 ps |
| T1085 |
/workspace/coverage/default/7.flash_ctrl_rw_serr.1237954465 |
|
|
Apr 16 01:29:52 PM PDT 24 |
Apr 16 01:40:06 PM PDT 24 |
6492289100 ps |
| T1086 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3520659990 |
|
|
Apr 16 01:34:27 PM PDT 24 |
Apr 16 01:35:53 PM PDT 24 |
2007207600 ps |
| T1087 |
/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.4180219390 |
|
|
Apr 16 01:32:20 PM PDT 24 |
Apr 16 01:32:50 PM PDT 24 |
42804700 ps |
| T1088 |
/workspace/coverage/default/43.flash_ctrl_otp_reset.68389405 |
|
|
Apr 16 01:38:18 PM PDT 24 |
Apr 16 01:40:27 PM PDT 24 |
136906200 ps |
| T1089 |
/workspace/coverage/default/11.flash_ctrl_intr_rd.3680191786 |
|
|
Apr 16 01:32:13 PM PDT 24 |
Apr 16 01:34:59 PM PDT 24 |
4293628500 ps |
| T1090 |
/workspace/coverage/default/27.flash_ctrl_sec_info_access.682224223 |
|
|
Apr 16 01:36:40 PM PDT 24 |
Apr 16 01:37:57 PM PDT 24 |
3825724300 ps |
| T1091 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1336296122 |
|
|
Apr 16 01:34:28 PM PDT 24 |
Apr 16 01:49:55 PM PDT 24 |
100161344500 ps |
| T1092 |
/workspace/coverage/default/37.flash_ctrl_intr_rd.707813004 |
|
|
Apr 16 01:37:55 PM PDT 24 |
Apr 16 01:41:38 PM PDT 24 |
4904145300 ps |
| T1093 |
/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2316135184 |
|
|
Apr 16 01:37:58 PM PDT 24 |
Apr 16 01:38:29 PM PDT 24 |
29974700 ps |
| T1094 |
/workspace/coverage/default/16.flash_ctrl_otp_reset.4192091466 |
|
|
Apr 16 01:34:08 PM PDT 24 |
Apr 16 01:36:19 PM PDT 24 |
291912300 ps |
| T1095 |
/workspace/coverage/default/6.flash_ctrl_intr_wr.2922085624 |
|
|
Apr 16 01:29:13 PM PDT 24 |
Apr 16 01:30:45 PM PDT 24 |
4208402000 ps |
| T1096 |
/workspace/coverage/default/50.flash_ctrl_otp_reset.2844212002 |
|
|
Apr 16 01:38:53 PM PDT 24 |
Apr 16 01:40:40 PM PDT 24 |
36007700 ps |
| T1097 |
/workspace/coverage/default/1.flash_ctrl_phy_arb.638826428 |
|
|
Apr 16 01:22:34 PM PDT 24 |
Apr 16 01:27:21 PM PDT 24 |
860582700 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_smoke_hw.428400390 |
|
|
Apr 16 01:22:29 PM PDT 24 |
Apr 16 01:22:53 PM PDT 24 |
25517400 ps |
| T1099 |
/workspace/coverage/default/2.flash_ctrl_serr_address.3207240231 |
|
|
Apr 16 01:24:33 PM PDT 24 |
Apr 16 01:26:09 PM PDT 24 |
3580487500 ps |
| T46 |
/workspace/coverage/default/1.flash_ctrl_access_after_disable.204231938 |
|
|
Apr 16 01:23:31 PM PDT 24 |
Apr 16 01:23:45 PM PDT 24 |
26160000 ps |
| T1100 |
/workspace/coverage/default/3.flash_ctrl_serr_counter.1071442300 |
|
|
Apr 16 01:26:07 PM PDT 24 |
Apr 16 01:27:02 PM PDT 24 |
422054700 ps |
| T1101 |
/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3225556798 |
|
|
Apr 16 01:26:53 PM PDT 24 |
Apr 16 01:28:14 PM PDT 24 |
1407766300 ps |
| T1102 |
/workspace/coverage/default/12.flash_ctrl_connect.1034053161 |
|
|
Apr 16 01:32:48 PM PDT 24 |
Apr 16 01:33:03 PM PDT 24 |
16486400 ps |
| T1103 |
/workspace/coverage/default/8.flash_ctrl_disable.1262159592 |
|
|
Apr 16 01:30:41 PM PDT 24 |
Apr 16 01:31:03 PM PDT 24 |
14367500 ps |
| T1104 |
/workspace/coverage/default/16.flash_ctrl_re_evict.1647665992 |
|
|
Apr 16 01:34:17 PM PDT 24 |
Apr 16 01:34:55 PM PDT 24 |
419073400 ps |
| T1105 |
/workspace/coverage/default/38.flash_ctrl_disable.661825797 |
|
|
Apr 16 01:38:01 PM PDT 24 |
Apr 16 01:38:23 PM PDT 24 |
10058100 ps |
| T274 |
/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.4145065613 |
|
|
Apr 16 01:24:07 PM PDT 24 |
Apr 16 01:25:47 PM PDT 24 |
83787900 ps |
| T1106 |
/workspace/coverage/default/42.flash_ctrl_smoke.3453593777 |
|
|
Apr 16 01:38:20 PM PDT 24 |
Apr 16 01:39:57 PM PDT 24 |
50384400 ps |
| T1107 |
/workspace/coverage/default/23.flash_ctrl_connect.3392016452 |
|
|
Apr 16 01:36:00 PM PDT 24 |
Apr 16 01:36:14 PM PDT 24 |
15465100 ps |
| T1108 |
/workspace/coverage/default/6.flash_ctrl_wo.28651295 |
|
|
Apr 16 01:28:48 PM PDT 24 |
Apr 16 01:30:50 PM PDT 24 |
6860379200 ps |
| T1109 |
/workspace/coverage/default/44.flash_ctrl_alert_test.3489513751 |
|
|
Apr 16 01:38:30 PM PDT 24 |
Apr 16 01:38:45 PM PDT 24 |
55783300 ps |
| T1110 |
/workspace/coverage/default/23.flash_ctrl_alert_test.3516660143 |
|
|
Apr 16 01:36:00 PM PDT 24 |
Apr 16 01:36:15 PM PDT 24 |
164965000 ps |
| T1111 |
/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2735635571 |
|
|
Apr 16 01:27:58 PM PDT 24 |
Apr 16 01:29:54 PM PDT 24 |
4669919300 ps |
| T275 |
/workspace/coverage/default/4.flash_ctrl_host_dir_rd.1167448536 |
|
|
Apr 16 01:26:48 PM PDT 24 |
Apr 16 01:28:06 PM PDT 24 |
125635400 ps |
| T1112 |
/workspace/coverage/default/9.flash_ctrl_phy_arb.2561792106 |
|
|
Apr 16 01:30:49 PM PDT 24 |
Apr 16 01:34:44 PM PDT 24 |
162849000 ps |
| T1113 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.2239640773 |
|
|
Apr 16 01:34:44 PM PDT 24 |
Apr 16 01:34:58 PM PDT 24 |
21283600 ps |
| T1114 |
/workspace/coverage/default/2.flash_ctrl_ro_derr.1845532722 |
|
|
Apr 16 01:24:38 PM PDT 24 |
Apr 16 01:27:00 PM PDT 24 |
1370344300 ps |
| T1115 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3900955259 |
|
|
Apr 16 01:35:47 PM PDT 24 |
Apr 16 01:38:54 PM PDT 24 |
8996760000 ps |
| T1116 |
/workspace/coverage/default/7.flash_ctrl_rw.3179948597 |
|
|
Apr 16 01:29:51 PM PDT 24 |
Apr 16 01:38:06 PM PDT 24 |
6696874100 ps |
| T1117 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.753804833 |
|
|
Apr 16 01:33:53 PM PDT 24 |
Apr 16 01:34:26 PM PDT 24 |
201761200 ps |
| T1118 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.2261056623 |
|
|
Apr 16 01:20:46 PM PDT 24 |
Apr 16 01:25:01 PM PDT 24 |
4098837300 ps |
| T1119 |
/workspace/coverage/default/4.flash_ctrl_connect.1810143267 |
|
|
Apr 16 01:27:45 PM PDT 24 |
Apr 16 01:28:01 PM PDT 24 |
81862100 ps |
| T1120 |
/workspace/coverage/default/29.flash_ctrl_disable.2548188947 |
|
|
Apr 16 01:36:53 PM PDT 24 |
Apr 16 01:37:16 PM PDT 24 |
26564000 ps |
| T1121 |
/workspace/coverage/default/45.flash_ctrl_disable.1739653288 |
|
|
Apr 16 01:38:40 PM PDT 24 |
Apr 16 01:39:03 PM PDT 24 |
17403300 ps |
| T1122 |
/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.4286543039 |
|
|
Apr 16 01:22:34 PM PDT 24 |
Apr 16 01:25:02 PM PDT 24 |
722354000 ps |
| T1123 |
/workspace/coverage/default/26.flash_ctrl_otp_reset.2805152 |
|
|
Apr 16 01:36:27 PM PDT 24 |
Apr 16 01:38:39 PM PDT 24 |
40760500 ps |
| T1124 |
/workspace/coverage/default/37.flash_ctrl_alert_test.1058392292 |
|
|
Apr 16 01:37:58 PM PDT 24 |
Apr 16 01:38:12 PM PDT 24 |
83633400 ps |
| T1125 |
/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1885739957 |
|
|
Apr 16 01:22:19 PM PDT 24 |
Apr 16 01:23:29 PM PDT 24 |
10018923500 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1422881756 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:44 PM PDT 24 |
94855000 ps |
| T64 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2209187969 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
39144300 ps |
| T65 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3946923011 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:52:02 PM PDT 24 |
192509600 ps |
| T259 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3860058049 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:45 PM PDT 24 |
29901800 ps |
| T179 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2514355401 |
|
|
Apr 16 02:51:01 PM PDT 24 |
Apr 16 02:51:54 PM PDT 24 |
465372300 ps |
| T180 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2693090530 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:59:02 PM PDT 24 |
213681000 ps |
| T214 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2149535570 |
|
|
Apr 16 02:51:15 PM PDT 24 |
Apr 16 02:52:12 PM PDT 24 |
10319971300 ps |
| T182 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.316511064 |
|
|
Apr 16 02:51:03 PM PDT 24 |
Apr 16 02:51:23 PM PDT 24 |
196100400 ps |
| T257 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1381033404 |
|
|
Apr 16 02:51:00 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
656153500 ps |
| T250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1985561856 |
|
|
Apr 16 02:51:14 PM PDT 24 |
Apr 16 02:51:32 PM PDT 24 |
459702300 ps |
| T1126 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.108217181 |
|
|
Apr 16 02:51:06 PM PDT 24 |
Apr 16 02:51:20 PM PDT 24 |
35065100 ps |
| T251 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3697170755 |
|
|
Apr 16 02:51:00 PM PDT 24 |
Apr 16 02:51:17 PM PDT 24 |
156833600 ps |
| T260 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2870809421 |
|
|
Apr 16 02:51:32 PM PDT 24 |
Apr 16 02:51:47 PM PDT 24 |
65019700 ps |
| T261 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4276190385 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:36 PM PDT 24 |
29955800 ps |
| T256 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1661804721 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
155594500 ps |
| T318 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4087973519 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
32583400 ps |
| T181 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1314386089 |
|
|
Apr 16 02:51:11 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
175634100 ps |
| T212 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.609493456 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 03:06:10 PM PDT 24 |
2615457000 ps |
| T225 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.260912260 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:36 PM PDT 24 |
49176300 ps |
| T319 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2544376 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
67370900 ps |
| T321 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3252935293 |
|
|
Apr 16 02:51:33 PM PDT 24 |
Apr 16 02:51:48 PM PDT 24 |
31858300 ps |
| T1127 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3861705039 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:51:51 PM PDT 24 |
25947300 ps |
| T1128 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3999437408 |
|
|
Apr 16 02:51:15 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
39830700 ps |
| T320 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2050471757 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:47 PM PDT 24 |
150081500 ps |
| T1129 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1475830753 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
331319000 ps |
| T294 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3450795485 |
|
|
Apr 16 02:51:13 PM PDT 24 |
Apr 16 02:52:03 PM PDT 24 |
3227235100 ps |
| T226 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1320397350 |
|
|
Apr 16 02:51:05 PM PDT 24 |
Apr 16 02:57:30 PM PDT 24 |
309614500 ps |
| T1130 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2603845256 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:51:44 PM PDT 24 |
11397900 ps |
| T1131 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.590759679 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:44 PM PDT 24 |
277840100 ps |
| T322 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4186606622 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:33 PM PDT 24 |
16651400 ps |
| T295 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2243340368 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
147199000 ps |
| T1132 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2238331931 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:45 PM PDT 24 |
673950200 ps |
| T323 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.170544741 |
|
|
Apr 16 02:51:17 PM PDT 24 |
Apr 16 02:51:31 PM PDT 24 |
42382900 ps |
| T213 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1290938949 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:51 PM PDT 24 |
275298400 ps |
| T324 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1896740510 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
42261700 ps |
| T296 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3736166213 |
|
|
Apr 16 02:51:11 PM PDT 24 |
Apr 16 02:51:29 PM PDT 24 |
400130200 ps |
| T297 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1803020602 |
|
|
Apr 16 02:51:13 PM PDT 24 |
Apr 16 02:51:33 PM PDT 24 |
120464500 ps |
| T231 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.24461210 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:59:01 PM PDT 24 |
506072400 ps |
| T1133 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1433098121 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:35 PM PDT 24 |
35964600 ps |
| T232 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4289271356 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:59:10 PM PDT 24 |
349276600 ps |
| T1134 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3268633143 |
|
|
Apr 16 02:51:05 PM PDT 24 |
Apr 16 02:51:19 PM PDT 24 |
40593800 ps |
| T1135 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3489676020 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
57982600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4123906346 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:51:51 PM PDT 24 |
16313600 ps |
| T227 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1834860964 |
|
|
Apr 16 02:51:24 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
308369700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3493701742 |
|
|
Apr 16 02:50:59 PM PDT 24 |
Apr 16 02:51:16 PM PDT 24 |
31643900 ps |
| T298 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1254058443 |
|
|
Apr 16 02:51:02 PM PDT 24 |
Apr 16 02:51:21 PM PDT 24 |
73434300 ps |
| T228 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.754654648 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
189989000 ps |
| T229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.79348271 |
|
|
Apr 16 02:50:57 PM PDT 24 |
Apr 16 02:51:16 PM PDT 24 |
48492500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1931124607 |
|
|
Apr 16 02:51:05 PM PDT 24 |
Apr 16 02:51:21 PM PDT 24 |
20692300 ps |
| T230 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3364813933 |
|
|
Apr 16 02:51:21 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
89398100 ps |
| T237 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2593936479 |
|
|
Apr 16 02:51:12 PM PDT 24 |
Apr 16 02:51:26 PM PDT 24 |
15345100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3783814273 |
|
|
Apr 16 02:51:06 PM PDT 24 |
Apr 16 02:51:20 PM PDT 24 |
12594900 ps |
| T233 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1622726664 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:38 PM PDT 24 |
40310500 ps |
| T1140 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2495384407 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
79895900 ps |
| T1141 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3488711393 |
|
|
Apr 16 02:51:09 PM PDT 24 |
Apr 16 02:52:15 PM PDT 24 |
1285824700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2387447299 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:51:44 PM PDT 24 |
14726400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1405336016 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
95913300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.929325990 |
|
|
Apr 16 02:51:08 PM PDT 24 |
Apr 16 02:51:21 PM PDT 24 |
18107900 ps |
| T1145 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1217470538 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
28254400 ps |
| T1146 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2021436106 |
|
|
Apr 16 02:51:04 PM PDT 24 |
Apr 16 02:51:17 PM PDT 24 |
21880900 ps |
| T1147 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2581876413 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
97792700 ps |
| T1148 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2303846452 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:43 PM PDT 24 |
30374800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3389165887 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
27443300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1993464881 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:48 PM PDT 24 |
17165500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2477891623 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
41099900 ps |
| T258 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.99078065 |
|
|
Apr 16 02:51:11 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
56364500 ps |
| T238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.141513848 |
|
|
Apr 16 02:50:57 PM PDT 24 |
Apr 16 02:51:11 PM PDT 24 |
57478900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2364260020 |
|
|
Apr 16 02:51:07 PM PDT 24 |
Apr 16 02:51:33 PM PDT 24 |
40088800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3157828602 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:34 PM PDT 24 |
23864200 ps |
| T268 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1615858580 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 03:03:56 PM PDT 24 |
4771706000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4201604487 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
57217800 ps |
| T1155 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3375564040 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:36 PM PDT 24 |
44692700 ps |
| T266 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1388898378 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:44 PM PDT 24 |
79973000 ps |
| T1156 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.373191418 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
31222100 ps |
| T1157 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2501345475 |
|
|
Apr 16 02:51:15 PM PDT 24 |
Apr 16 02:51:31 PM PDT 24 |
33504200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1508796150 |
|
|
Apr 16 02:51:11 PM PDT 24 |
Apr 16 02:51:57 PM PDT 24 |
390055000 ps |
| T1159 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1390766517 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:45 PM PDT 24 |
26156000 ps |
| T1160 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3102537191 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:43 PM PDT 24 |
19471100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3063275430 |
|
|
Apr 16 02:51:06 PM PDT 24 |
Apr 16 02:51:59 PM PDT 24 |
6643994200 ps |
| T262 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2079169112 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
189705400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1218978244 |
|
|
Apr 16 02:50:58 PM PDT 24 |
Apr 16 02:51:13 PM PDT 24 |
50228600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1266493391 |
|
|
Apr 16 02:51:05 PM PDT 24 |
Apr 16 02:51:23 PM PDT 24 |
97473200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3444851796 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
48369500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1886281648 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:45 PM PDT 24 |
29176800 ps |
| T263 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4218402187 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
256041700 ps |
| T299 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2662851472 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 03:06:25 PM PDT 24 |
3718864100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4248152286 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:33 PM PDT 24 |
65710500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1359457877 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
29363800 ps |
| T1168 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3085065998 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:46 PM PDT 24 |
92827200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2633929789 |
|
|
Apr 16 02:51:33 PM PDT 24 |
Apr 16 02:51:48 PM PDT 24 |
32007000 ps |
| T1170 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.294086683 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:44 PM PDT 24 |
19480900 ps |
| T239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.924330799 |
|
|
Apr 16 02:51:02 PM PDT 24 |
Apr 16 02:51:16 PM PDT 24 |
167467100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1407131571 |
|
|
Apr 16 02:51:00 PM PDT 24 |
Apr 16 02:51:15 PM PDT 24 |
46167500 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3427468836 |
|
|
Apr 16 02:51:09 PM PDT 24 |
Apr 16 02:51:23 PM PDT 24 |
29267200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2113081413 |
|
|
Apr 16 02:51:02 PM PDT 24 |
Apr 16 02:51:18 PM PDT 24 |
44837200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4028417523 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
57678400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.780339995 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
23645300 ps |
| T1176 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2972124071 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:38 PM PDT 24 |
18467100 ps |
| T352 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3710808249 |
|
|
Apr 16 02:51:04 PM PDT 24 |
Apr 16 03:06:11 PM PDT 24 |
2796063200 ps |
| T356 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2969477478 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 03:06:12 PM PDT 24 |
1474090600 ps |
| T1177 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3539732778 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:51:52 PM PDT 24 |
178905700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2411169373 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
616961700 ps |
| T1179 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4234384249 |
|
|
Apr 16 02:51:12 PM PDT 24 |
Apr 16 02:51:26 PM PDT 24 |
36775000 ps |
| T264 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1099727177 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:43 PM PDT 24 |
99520500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3482261042 |
|
|
Apr 16 02:51:17 PM PDT 24 |
Apr 16 02:51:36 PM PDT 24 |
140890800 ps |
| T1181 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.802367620 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
24396300 ps |
| T240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1388955652 |
|
|
Apr 16 02:51:16 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
17686900 ps |
| T1182 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.63810819 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
16311800 ps |
| T1183 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2595666354 |
|
|
Apr 16 02:50:56 PM PDT 24 |
Apr 16 02:51:13 PM PDT 24 |
21059900 ps |
| T1184 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3441542263 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
32319000 ps |
| T241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4265267591 |
|
|
Apr 16 02:51:06 PM PDT 24 |
Apr 16 02:51:21 PM PDT 24 |
49699800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3499570579 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:46 PM PDT 24 |
17147000 ps |
| T267 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4245715101 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
50418400 ps |
| T357 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.542514597 |
|
|
Apr 16 02:51:11 PM PDT 24 |
Apr 16 03:06:09 PM PDT 24 |
1708996900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2510809586 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:46 PM PDT 24 |
48227300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2980104661 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
17352900 ps |
| T351 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.434065507 |
|
|
Apr 16 02:50:58 PM PDT 24 |
Apr 16 02:57:26 PM PDT 24 |
552235700 ps |
| T358 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2147187763 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:58:52 PM PDT 24 |
668865800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3047078757 |
|
|
Apr 16 02:51:33 PM PDT 24 |
Apr 16 02:51:48 PM PDT 24 |
25243300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1473767408 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:51:52 PM PDT 24 |
17633600 ps |
| T1190 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3827575233 |
|
|
Apr 16 02:51:01 PM PDT 24 |
Apr 16 02:51:15 PM PDT 24 |
37506300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4265894165 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:47 PM PDT 24 |
16907900 ps |
| T1192 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2457419178 |
|
|
Apr 16 02:50:59 PM PDT 24 |
Apr 16 02:51:45 PM PDT 24 |
237518900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3638144652 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:34 PM PDT 24 |
30365200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3423799519 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:49 PM PDT 24 |
30560400 ps |
| T1195 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2431687221 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 03:06:17 PM PDT 24 |
1509503800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.48772073 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:51 PM PDT 24 |
68423400 ps |
| T1197 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4284691758 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
15545400 ps |
| T300 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.538979504 |
|
|
Apr 16 02:51:00 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
904603400 ps |
| T1198 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.26416781 |
|
|
Apr 16 02:51:33 PM PDT 24 |
Apr 16 02:51:48 PM PDT 24 |
15808400 ps |
| T301 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2624583940 |
|
|
Apr 16 02:50:59 PM PDT 24 |
Apr 16 02:51:19 PM PDT 24 |
120059000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2472530016 |
|
|
Apr 16 02:51:00 PM PDT 24 |
Apr 16 02:51:16 PM PDT 24 |
394879600 ps |
| T1200 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2418601600 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:47 PM PDT 24 |
75901500 ps |
| T265 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4616958 |
|
|
Apr 16 02:51:12 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
41694300 ps |
| T1201 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2953601312 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
25267900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1368281529 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
55119800 ps |
| T302 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2483402269 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
1144297300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1107265752 |
|
|
Apr 16 02:51:09 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
347233400 ps |
| T1204 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2680693395 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:43 PM PDT 24 |
18656800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.657682341 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
1128410000 ps |
| T1206 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3608225914 |
|
|
Apr 16 02:51:24 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
38856900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3613042677 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 02:51:45 PM PDT 24 |
18120100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3267982200 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:46 PM PDT 24 |
16535300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4220422477 |
|
|
Apr 16 02:51:03 PM PDT 24 |
Apr 16 02:52:07 PM PDT 24 |
2524760600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.381326537 |
|
|
Apr 16 02:51:01 PM PDT 24 |
Apr 16 02:51:15 PM PDT 24 |
17951400 ps |
| T1211 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2535742240 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
17898300 ps |
| T1212 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3432947111 |
|
|
Apr 16 02:51:24 PM PDT 24 |
Apr 16 02:51:38 PM PDT 24 |
17464400 ps |
| T354 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2989451736 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 03:03:55 PM PDT 24 |
1001727900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.975140728 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
31131800 ps |
| T353 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2289851389 |
|
|
Apr 16 02:51:28 PM PDT 24 |
Apr 16 03:06:19 PM PDT 24 |
812408100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2843573171 |
|
|
Apr 16 02:51:13 PM PDT 24 |
Apr 16 02:51:27 PM PDT 24 |
15896900 ps |
| T1215 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.206442577 |
|
|
Apr 16 02:51:27 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
18625700 ps |
| T1216 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.878262186 |
|
|
Apr 16 02:51:22 PM PDT 24 |
Apr 16 02:59:02 PM PDT 24 |
468937300 ps |
| T1217 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.196012795 |
|
|
Apr 16 02:51:33 PM PDT 24 |
Apr 16 02:51:48 PM PDT 24 |
27300500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3413136653 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:34 PM PDT 24 |
12955800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2372935913 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
56708700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2311387224 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:39 PM PDT 24 |
17346600 ps |
| T1221 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2148906034 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:38 PM PDT 24 |
102937300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3696993623 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
77308400 ps |
| T1223 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3565474017 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:43 PM PDT 24 |
26374500 ps |
| T360 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2236634279 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 03:03:51 PM PDT 24 |
1313981200 ps |
| T1224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.64459975 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
46723100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.973740714 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:35 PM PDT 24 |
57385200 ps |
| T1226 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1999795137 |
|
|
Apr 16 02:51:06 PM PDT 24 |
Apr 16 02:51:21 PM PDT 24 |
45943300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2130789540 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:32 PM PDT 24 |
12347900 ps |
| T355 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.289163168 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:57:45 PM PDT 24 |
220530800 ps |
| T1228 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1627847167 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
1286164700 ps |
| T1229 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1018228495 |
|
|
Apr 16 02:51:24 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
67235600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.362476775 |
|
|
Apr 16 02:51:25 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
23711500 ps |
| T1231 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3964493689 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:43 PM PDT 24 |
225002900 ps |
| T1232 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.194717088 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:35 PM PDT 24 |
11643100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.91253903 |
|
|
Apr 16 02:51:19 PM PDT 24 |
Apr 16 02:51:36 PM PDT 24 |
65960100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2133567826 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:37 PM PDT 24 |
47209100 ps |
| T1235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4057797014 |
|
|
Apr 16 02:51:09 PM PDT 24 |
Apr 16 02:51:25 PM PDT 24 |
64131600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1520532561 |
|
|
Apr 16 02:51:14 PM PDT 24 |
Apr 16 02:51:28 PM PDT 24 |
46277000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3815266758 |
|
|
Apr 16 02:51:20 PM PDT 24 |
Apr 16 02:51:38 PM PDT 24 |
92866700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3769324237 |
|
|
Apr 16 02:51:18 PM PDT 24 |
Apr 16 02:51:35 PM PDT 24 |
12326500 ps |
| T1239 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.169642772 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:51:53 PM PDT 24 |
215298900 ps |
| T1240 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3634966560 |
|
|
Apr 16 02:51:17 PM PDT 24 |
Apr 16 02:51:34 PM PDT 24 |
36772300 ps |
| T1241 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3070136898 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:42 PM PDT 24 |
45008500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2297344481 |
|
|
Apr 16 02:51:16 PM PDT 24 |
Apr 16 02:51:30 PM PDT 24 |
119898600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3126111881 |
|
|
Apr 16 02:51:34 PM PDT 24 |
Apr 16 02:51:50 PM PDT 24 |
228088600 ps |
| T1244 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.4126877231 |
|
|
Apr 16 02:51:05 PM PDT 24 |
Apr 16 02:51:19 PM PDT 24 |
31696600 ps |
| T359 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1920929286 |
|
|
Apr 16 02:51:24 PM PDT 24 |
Apr 16 02:59:02 PM PDT 24 |
1495348100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1547733371 |
|
|
Apr 16 02:51:09 PM PDT 24 |
Apr 16 02:51:23 PM PDT 24 |
13967000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.577819764 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:41 PM PDT 24 |
428179700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1137577808 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:46 PM PDT 24 |
50878900 ps |
| T303 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4163510594 |
|
|
Apr 16 02:51:31 PM PDT 24 |
Apr 16 02:51:49 PM PDT 24 |
57623200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2739770578 |
|
|
Apr 16 02:51:30 PM PDT 24 |
Apr 16 02:51:47 PM PDT 24 |
48637700 ps |
| T1249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1807489652 |
|
|
Apr 16 02:51:02 PM PDT 24 |
Apr 16 02:51:22 PM PDT 24 |
442632400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1159928571 |
|
|
Apr 16 02:51:23 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
15271000 ps |
| T1251 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3874957044 |
|
|
Apr 16 02:51:26 PM PDT 24 |
Apr 16 02:51:40 PM PDT 24 |
47963300 ps |