Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	313821	1		T1	2		T2	2		T3	3361
all_values[1]	313821	1		T1	2		T2	2		T3	3361
all_values[2]	313821	1		T1	2		T2	2		T3	3361
all_values[3]	313821	1		T1	2		T2	2		T3	3361
all_values[4]	313821	1		T1	2		T2	2		T3	3361
all_values[5]	313821	1		T1	2		T2	2		T3	3361

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	634254	1		T1	12		T2	12		T3	6726
auto[1]	1248672	1		T3	13440		T19	4700		T31	9168

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	915378	1		T1	6		T2	7		T3	9244
auto[1]	967548	1		T1	6		T2	5		T3	10922

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	313688	1		T1	2		T2	2		T3	3361
all_values[0]	auto[1]	auto[1]	133	1		T268	3		T269	2		T317	4
all_values[1]	auto[0]	auto[1]	313648	1		T1	2		T2	2		T3	3361
all_values[1]	auto[1]	auto[1]	173	1		T268	3		T269	5		T317	3
all_values[2]	auto[0]	auto[0]	1691	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	58	1		T269	1		T317	2		T318	1
all_values[2]	auto[1]	auto[0]	312029	1		T3	3360		T19	1175		T31	2292
all_values[2]	auto[1]	auto[1]	43	1		T319	2		T321	1		T332	1
all_values[3]	auto[0]	auto[0]	1670	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	60	1		T269	1		T317	1		T318	3
all_values[3]	auto[1]	auto[0]	69990	1		T19	1175		T31	1146		T25	1021
all_values[3]	auto[1]	auto[1]	242101	1		T3	3360		T31	1146		T32	1914
all_values[4]	auto[0]	auto[0]	1163	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	553	1		T1	1		T2	1		T4	1
all_values[4]	auto[1]	auto[0]	215215	1		T3	2520		T19	1		T31	1146
all_values[4]	auto[1]	auto[1]	96890	1		T3	840		T19	1174		T31	1146
all_values[5]	auto[0]	auto[0]	1582	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	141	1		T1	1		T21	1		T33	1
all_values[5]	auto[1]	auto[0]	312038	1		T3	3360		T19	1175		T31	2292
all_values[5]	auto[1]	auto[1]	60	1		T269	1		T317	1		T318	3