Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T103 |
1 |
|
T115 |
9 |
|
T99 |
1 |
| others[1] |
208 |
1 |
|
T115 |
9 |
|
T67 |
11 |
|
T384 |
1 |
| others[2] |
206 |
1 |
|
T115 |
6 |
|
T378 |
1 |
|
T212 |
1 |
| others[3] |
397 |
1 |
|
T21 |
1 |
|
T131 |
1 |
|
T115 |
21 |
| false |
119 |
1 |
|
T33 |
1 |
|
T115 |
2 |
|
T376 |
1 |
| true |
13370 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8871 |
1 |
|
T3 |
1 |
|
T16 |
125 |
|
T17 |
1 |
| others[1] |
1271 |
1 |
|
T5 |
1 |
|
T39 |
11 |
|
T114 |
1 |
| others[2] |
1252 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T39 |
6 |
| others[3] |
2040 |
1 |
|
T5 |
2 |
|
T38 |
1 |
|
T25 |
1 |
| false |
642 |
1 |
|
T5 |
1 |
|
T39 |
7 |
|
T103 |
1 |
| true |
445 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8878 |
1 |
|
T16 |
125 |
|
T5 |
5 |
|
T24 |
1 |
| others[1] |
1244 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T39 |
6 |
| others[2] |
1247 |
1 |
|
T15 |
1 |
|
T39 |
5 |
|
T63 |
3 |
| others[3] |
2123 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T18 |
1 |
| false |
610 |
1 |
|
T2 |
1 |
|
T25 |
1 |
|
T39 |
6 |
| true |
419 |
1 |
|
T1 |
1 |
|
T22 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T103 |
1 |
|
T115 |
6 |
|
T99 |
1 |
| others[1] |
108 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
2 |
| others[2] |
99 |
1 |
|
T316 |
1 |
|
T376 |
1 |
|
T372 |
1 |
| others[3] |
188 |
1 |
|
T2 |
1 |
|
T131 |
1 |
|
T115 |
10 |
| false |
70 |
1 |
|
T115 |
5 |
|
T372 |
1 |
|
T99 |
1 |
| true |
13949 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T131 |
1 |
|
T115 |
16 |
|
T280 |
1 |
| others[1] |
211 |
1 |
|
T21 |
1 |
|
T42 |
1 |
|
T130 |
1 |
| others[2] |
226 |
1 |
|
T24 |
1 |
|
T103 |
1 |
|
T29 |
1 |
| others[3] |
411 |
1 |
|
T23 |
1 |
|
T28 |
1 |
|
T131 |
1 |
| false |
110 |
1 |
|
T22 |
1 |
|
T43 |
1 |
|
T34 |
1 |
| true |
13310 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8690 |
1 |
|
T16 |
125 |
|
T5 |
6 |
|
T38 |
1 |
| others[1] |
1108 |
1 |
|
T5 |
2 |
|
T18 |
1 |
|
T23 |
1 |
| others[2] |
1011 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[3] |
1782 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
566 |
1 |
|
T39 |
6 |
|
T103 |
1 |
|
T87 |
1 |
| true |
1364 |
1 |
|
T22 |
1 |
|
T24 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T31 |
1 |
|
T33 |
1 |
|
T136 |
1 |
| others[1] |
243 |
1 |
|
T103 |
1 |
|
T115 |
7 |
|
T374 |
1 |
| others[2] |
231 |
1 |
|
T22 |
1 |
|
T115 |
12 |
|
T35 |
1 |
| others[3] |
385 |
1 |
|
T15 |
1 |
|
T51 |
1 |
|
T30 |
1 |
| false |
112 |
1 |
|
T115 |
10 |
|
T212 |
1 |
|
T67 |
2 |
| true |
13321 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
193 |
1 |
|
T131 |
1 |
|
T115 |
10 |
|
T375 |
1 |
| others[1] |
234 |
1 |
|
T115 |
13 |
|
T67 |
11 |
|
T384 |
2 |
| others[2] |
201 |
1 |
|
T2 |
1 |
|
T115 |
14 |
|
T99 |
1 |
| others[3] |
379 |
1 |
|
T115 |
16 |
|
T374 |
1 |
|
T376 |
1 |
| false |
107 |
1 |
|
T115 |
3 |
|
T212 |
1 |
|
T67 |
5 |
| true |
13407 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8856 |
1 |
|
T16 |
125 |
|
T5 |
1 |
|
T31 |
1 |
| others[1] |
1279 |
1 |
|
T5 |
4 |
|
T25 |
1 |
|
T39 |
5 |
| others[2] |
1255 |
1 |
|
T2 |
1 |
|
T39 |
11 |
|
T103 |
1 |
| others[3] |
2044 |
1 |
|
T5 |
4 |
|
T39 |
11 |
|
T40 |
1 |
| false |
653 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T19 |
1 |
| true |
434 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T5 |
3 |
|
T39 |
7 |
|
T167 |
1 |
| others[1] |
1301 |
1 |
|
T3 |
1 |
|
T5 |
4 |
|
T25 |
1 |
| others[2] |
1235 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
2 |
| others[3] |
2012 |
1 |
|
T38 |
1 |
|
T39 |
15 |
|
T114 |
1 |
| false |
677 |
1 |
|
T39 |
8 |
|
T113 |
7 |
|
T85 |
9 |
| true |
428 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T115 |
1 |
|
T375 |
1 |
|
T67 |
4 |
| others[1] |
117 |
1 |
|
T131 |
1 |
|
T115 |
2 |
|
T372 |
1 |
| others[2] |
110 |
1 |
|
T115 |
2 |
|
T67 |
5 |
|
T384 |
1 |
| others[3] |
185 |
1 |
|
T2 |
1 |
|
T103 |
2 |
|
T115 |
10 |
| false |
59 |
1 |
|
T131 |
1 |
|
T316 |
1 |
|
T372 |
1 |
| true |
6331 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T103 |
1 |
| others[1] |
217 |
1 |
|
T1 |
1 |
|
T131 |
1 |
|
T115 |
13 |
| others[2] |
256 |
1 |
|
T51 |
1 |
|
T131 |
1 |
|
T136 |
1 |
| others[3] |
408 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T115 |
14 |
| false |
97 |
1 |
|
T29 |
1 |
|
T115 |
8 |
|
T109 |
1 |
| true |
5677 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| others[1] |
1088 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T22 |
1 |
| others[2] |
1013 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[3] |
1736 |
1 |
|
T5 |
3 |
|
T38 |
1 |
|
T25 |
1 |
| false |
565 |
1 |
|
T5 |
2 |
|
T39 |
4 |
|
T41 |
1 |
| true |
1440 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T21 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| others[1] |
258 |
1 |
|
T18 |
1 |
|
T115 |
8 |
|
T35 |
1 |
| others[2] |
244 |
1 |
|
T115 |
10 |
|
T374 |
1 |
|
T278 |
1 |
| others[3] |
393 |
1 |
|
T22 |
1 |
|
T103 |
1 |
|
T28 |
1 |
| false |
114 |
1 |
|
T15 |
1 |
|
T42 |
1 |
|
T115 |
2 |
| true |
5677 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T131 |
1 |
|
T62 |
1 |
|
T115 |
6 |
| others[1] |
206 |
1 |
|
T115 |
10 |
|
T375 |
1 |
|
T372 |
1 |
| others[2] |
202 |
1 |
|
T115 |
14 |
|
T109 |
1 |
|
T304 |
1 |
| others[3] |
373 |
1 |
|
T131 |
1 |
|
T115 |
16 |
|
T212 |
1 |
| false |
119 |
1 |
|
T115 |
2 |
|
T218 |
1 |
|
T67 |
4 |
| true |
5800 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T25 |
1 |
| others[1] |
1257 |
1 |
|
T5 |
5 |
|
T39 |
8 |
|
T114 |
1 |
| others[2] |
1220 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
9 |
| others[3] |
2050 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T39 |
16 |
| false |
685 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T31 |
1 |
| true |
435 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T38 |
1 |
| others[1] |
1250 |
1 |
|
T5 |
2 |
|
T25 |
1 |
|
T39 |
10 |
| others[2] |
1230 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T39 |
8 |
| others[3] |
2108 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
2 |
| false |
640 |
1 |
|
T5 |
2 |
|
T39 |
1 |
|
T40 |
1 |
| true |
429 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
121 |
1 |
|
T103 |
1 |
|
T115 |
4 |
|
T67 |
3 |
| others[1] |
94 |
1 |
|
T115 |
4 |
|
T374 |
1 |
|
T99 |
1 |
| others[2] |
112 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T131 |
1 |
| others[3] |
183 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T62 |
1 |
| false |
51 |
1 |
|
T115 |
2 |
|
T67 |
1 |
|
T88 |
1 |
| true |
6337 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T42 |
1 |
|
T115 |
9 |
|
T375 |
1 |
| others[1] |
238 |
1 |
|
T33 |
1 |
|
T115 |
9 |
|
T116 |
1 |
| others[2] |
230 |
1 |
|
T61 |
1 |
|
T34 |
1 |
|
T28 |
1 |
| others[3] |
417 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T22 |
1 |
| false |
113 |
1 |
|
T115 |
4 |
|
T216 |
1 |
|
T306 |
1 |
| true |
5649 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
997 |
1 |
|
T38 |
1 |
|
T39 |
12 |
|
T33 |
1 |
| others[1] |
1045 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
1079 |
1 |
|
T19 |
1 |
|
T39 |
7 |
|
T41 |
1 |
| others[3] |
1786 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
7 |
| false |
554 |
1 |
|
T5 |
1 |
|
T22 |
1 |
|
T39 |
5 |
| true |
1437 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T21 |
1 |
| others[1] |
221 |
1 |
|
T1 |
1 |
|
T115 |
10 |
|
T306 |
1 |
| others[2] |
238 |
1 |
|
T18 |
1 |
|
T131 |
1 |
|
T115 |
9 |
| others[3] |
381 |
1 |
|
T115 |
12 |
|
T375 |
1 |
|
T278 |
1 |
| false |
116 |
1 |
|
T136 |
1 |
|
T115 |
6 |
|
T376 |
1 |
| true |
5701 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T1 |
1 |
|
T115 |
11 |
|
T378 |
1 |
| others[1] |
205 |
1 |
|
T131 |
2 |
|
T115 |
8 |
|
T376 |
1 |
| others[2] |
221 |
1 |
|
T115 |
11 |
|
T373 |
1 |
|
T67 |
14 |
| others[3] |
354 |
1 |
|
T18 |
1 |
|
T115 |
13 |
|
T375 |
1 |
| false |
112 |
1 |
|
T115 |
4 |
|
T214 |
1 |
|
T67 |
4 |
| true |
5752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| others[1] |
1207 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
10 |
| others[2] |
1242 |
1 |
|
T31 |
1 |
|
T39 |
5 |
|
T103 |
1 |
| others[3] |
2147 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
4 |
| false |
603 |
1 |
|
T5 |
2 |
|
T38 |
1 |
|
T21 |
1 |
| true |
444 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[1] |
1261 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T25 |
1 |
| others[2] |
1234 |
1 |
|
T17 |
1 |
|
T5 |
4 |
|
T38 |
1 |
| others[3] |
2046 |
1 |
|
T5 |
2 |
|
T31 |
1 |
|
T39 |
10 |
| false |
657 |
1 |
|
T5 |
1 |
|
T39 |
3 |
|
T114 |
1 |
| true |
433 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
118 |
1 |
|
T131 |
1 |
|
T115 |
4 |
|
T372 |
1 |
| others[1] |
98 |
1 |
|
T103 |
1 |
|
T115 |
3 |
|
T372 |
1 |
| others[2] |
102 |
1 |
|
T131 |
1 |
|
T115 |
5 |
|
T67 |
5 |
| others[3] |
200 |
1 |
|
T103 |
1 |
|
T115 |
9 |
|
T374 |
1 |
| false |
56 |
1 |
|
T2 |
1 |
|
T115 |
1 |
|
T99 |
1 |
| true |
6324 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T115 |
15 |
| others[1] |
236 |
1 |
|
T31 |
1 |
|
T115 |
10 |
|
T109 |
1 |
| others[2] |
250 |
1 |
|
T1 |
1 |
|
T43 |
1 |
|
T61 |
1 |
| others[3] |
394 |
1 |
|
T21 |
1 |
|
T34 |
1 |
|
T103 |
1 |
| false |
129 |
1 |
|
T42 |
1 |
|
T51 |
1 |
|
T130 |
1 |
| true |
5639 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T5 |
3 |
|
T38 |
1 |
|
T39 |
6 |
| others[1] |
1037 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T39 |
11 |
| others[2] |
1088 |
1 |
|
T5 |
2 |
|
T21 |
1 |
|
T39 |
10 |
| others[3] |
1745 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| false |
553 |
1 |
|
T2 |
1 |
|
T23 |
1 |
|
T39 |
3 |
| true |
1409 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T18 |
1 |
|
T103 |
1 |
|
T115 |
10 |
| others[1] |
205 |
1 |
|
T115 |
12 |
|
T117 |
1 |
|
T378 |
1 |
| others[2] |
244 |
1 |
|
T51 |
1 |
|
T29 |
1 |
|
T115 |
12 |
| others[3] |
419 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T130 |
1 |
| false |
126 |
1 |
|
T115 |
8 |
|
T211 |
1 |
|
T67 |
2 |
| true |
5670 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T115 |
7 |
|
T316 |
1 |
|
T375 |
1 |
| others[1] |
219 |
1 |
|
T1 |
1 |
|
T103 |
1 |
|
T115 |
8 |
| others[2] |
243 |
1 |
|
T21 |
1 |
|
T103 |
1 |
|
T115 |
9 |
| others[3] |
354 |
1 |
|
T131 |
1 |
|
T62 |
1 |
|
T115 |
13 |
| false |
106 |
1 |
|
T115 |
7 |
|
T211 |
1 |
|
T67 |
3 |
| true |
5750 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T17 |
1 |
|
T39 |
4 |
|
T167 |
1 |
| others[1] |
1272 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T39 |
11 |
| others[2] |
1205 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[3] |
2101 |
1 |
|
T5 |
4 |
|
T25 |
1 |
|
T39 |
15 |
| false |
605 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T39 |
5 |
| true |
444 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T39 |
10 |
| others[1] |
1236 |
1 |
|
T25 |
1 |
|
T39 |
9 |
|
T40 |
1 |
| others[2] |
1239 |
1 |
|
T5 |
2 |
|
T39 |
5 |
|
T167 |
1 |
| others[3] |
2104 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
3 |
| false |
627 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T5 |
2 |
| true |
422 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T22 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |