Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T115 |
2 |
|
T67 |
8 |
|
T384 |
1 |
| others[1] |
107 |
1 |
|
T2 |
1 |
|
T103 |
1 |
|
T131 |
1 |
| others[2] |
110 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
2 |
| others[3] |
186 |
1 |
|
T115 |
3 |
|
T376 |
1 |
|
T372 |
1 |
| false |
46 |
1 |
|
T372 |
1 |
|
T67 |
1 |
|
T88 |
1 |
| true |
6344 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T33 |
1 |
|
T43 |
1 |
|
T115 |
10 |
| others[1] |
260 |
1 |
|
T61 |
1 |
|
T30 |
1 |
|
T115 |
12 |
| others[2] |
258 |
1 |
|
T15 |
1 |
|
T42 |
1 |
|
T131 |
1 |
| others[3] |
397 |
1 |
|
T1 |
1 |
|
T22 |
1 |
|
T34 |
1 |
| false |
116 |
1 |
|
T136 |
1 |
|
T115 |
5 |
|
T109 |
1 |
| true |
5640 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1088 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T18 |
1 |
| others[1] |
1081 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T39 |
4 |
| others[2] |
1059 |
1 |
|
T22 |
1 |
|
T39 |
8 |
|
T103 |
1 |
| others[3] |
1741 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| false |
575 |
1 |
|
T5 |
2 |
|
T39 |
3 |
|
T10 |
1 |
| true |
1354 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T15 |
1 |
|
T131 |
1 |
|
T115 |
11 |
| others[1] |
239 |
1 |
|
T33 |
1 |
|
T115 |
14 |
|
T67 |
13 |
| others[2] |
227 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T31 |
1 |
| others[3] |
387 |
1 |
|
T22 |
1 |
|
T51 |
1 |
|
T103 |
1 |
| false |
120 |
1 |
|
T103 |
1 |
|
T115 |
1 |
|
T375 |
1 |
| true |
5689 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T1 |
1 |
|
T115 |
9 |
|
T316 |
1 |
| others[1] |
243 |
1 |
|
T103 |
1 |
|
T131 |
2 |
|
T115 |
10 |
| others[2] |
254 |
1 |
|
T33 |
1 |
|
T103 |
1 |
|
T115 |
13 |
| others[3] |
389 |
1 |
|
T115 |
18 |
|
T374 |
1 |
|
T378 |
1 |
| false |
120 |
1 |
|
T115 |
2 |
|
T67 |
6 |
|
T386 |
1 |
| true |
5671 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T3 |
1 |
|
T38 |
1 |
|
T39 |
7 |
| others[1] |
1281 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T39 |
6 |
| others[2] |
1167 |
1 |
|
T17 |
1 |
|
T5 |
3 |
|
T19 |
1 |
| others[3] |
2111 |
1 |
|
T5 |
4 |
|
T25 |
1 |
|
T39 |
17 |
| false |
644 |
1 |
|
T5 |
1 |
|
T39 |
4 |
|
T113 |
8 |
| true |
444 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T38 |
1 |
| others[1] |
1269 |
1 |
|
T5 |
4 |
|
T39 |
4 |
|
T40 |
1 |
| others[2] |
1218 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T39 |
8 |
| others[3] |
2095 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T39 |
10 |
| false |
640 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
9 |
| true |
419 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T131 |
1 |
|
T115 |
6 |
|
T374 |
1 |
| others[1] |
116 |
1 |
|
T2 |
1 |
|
T115 |
2 |
|
T214 |
1 |
| others[2] |
90 |
1 |
|
T103 |
1 |
|
T115 |
1 |
|
T372 |
1 |
| others[3] |
197 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
4 |
| false |
60 |
1 |
|
T115 |
5 |
|
T67 |
2 |
|
T88 |
1 |
| true |
6342 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T131 |
1 |
|
T115 |
14 |
|
T214 |
1 |
| others[1] |
242 |
1 |
|
T1 |
1 |
|
T103 |
1 |
|
T115 |
11 |
| others[2] |
240 |
1 |
|
T31 |
1 |
|
T29 |
1 |
|
T115 |
11 |
| others[3] |
452 |
1 |
|
T15 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| false |
118 |
1 |
|
T18 |
1 |
|
T131 |
1 |
|
T115 |
4 |
| true |
5605 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T38 |
1 |
| others[1] |
1052 |
1 |
|
T5 |
1 |
|
T39 |
12 |
|
T40 |
1 |
| others[2] |
1053 |
1 |
|
T5 |
5 |
|
T39 |
3 |
|
T41 |
1 |
| others[3] |
1807 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| false |
565 |
1 |
|
T2 |
1 |
|
T39 |
8 |
|
T167 |
1 |
| true |
1370 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T103 |
1 |
|
T29 |
1 |
|
T115 |
7 |
| others[1] |
234 |
1 |
|
T115 |
8 |
|
T216 |
1 |
|
T117 |
1 |
| others[2] |
254 |
1 |
|
T31 |
1 |
|
T115 |
15 |
|
T278 |
1 |
| others[3] |
380 |
1 |
|
T18 |
1 |
|
T42 |
1 |
|
T28 |
1 |
| false |
103 |
1 |
|
T103 |
1 |
|
T115 |
4 |
|
T378 |
1 |
| true |
5675 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T33 |
1 |
|
T115 |
8 |
|
T67 |
7 |
| others[1] |
231 |
1 |
|
T115 |
7 |
|
T67 |
6 |
|
T380 |
1 |
| others[2] |
219 |
1 |
|
T131 |
1 |
|
T115 |
4 |
|
T375 |
1 |
| others[3] |
361 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T131 |
1 |
| false |
118 |
1 |
|
T103 |
1 |
|
T115 |
5 |
|
T99 |
1 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T39 |
7 |
| others[1] |
1199 |
1 |
|
T5 |
1 |
|
T39 |
9 |
|
T61 |
1 |
| others[2] |
1288 |
1 |
|
T3 |
1 |
|
T5 |
5 |
|
T25 |
1 |
| others[3] |
2056 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| false |
659 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T39 |
3 |
| true |
433 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T5 |
3 |
|
T39 |
12 |
|
T10 |
1 |
| others[1] |
1277 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
3 |
| others[2] |
1223 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T39 |
5 |
| others[3] |
2040 |
1 |
|
T5 |
2 |
|
T25 |
1 |
|
T39 |
12 |
| false |
676 |
1 |
|
T17 |
1 |
|
T39 |
7 |
|
T167 |
1 |
| true |
433 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
124 |
1 |
|
T103 |
2 |
|
T131 |
1 |
|
T115 |
5 |
| others[1] |
119 |
1 |
|
T2 |
1 |
|
T131 |
1 |
|
T115 |
7 |
| others[2] |
98 |
1 |
|
T62 |
1 |
|
T115 |
2 |
|
T67 |
2 |
| others[3] |
176 |
1 |
|
T115 |
8 |
|
T316 |
1 |
|
T372 |
1 |
| false |
57 |
1 |
|
T99 |
1 |
|
T67 |
2 |
|
T384 |
1 |
| true |
6324 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T115 |
13 |
|
T337 |
1 |
|
T379 |
1 |
| others[1] |
252 |
1 |
|
T18 |
1 |
|
T29 |
1 |
|
T115 |
9 |
| others[2] |
229 |
1 |
|
T23 |
1 |
|
T33 |
1 |
|
T115 |
9 |
| others[3] |
408 |
1 |
|
T15 |
1 |
|
T22 |
1 |
|
T24 |
1 |
| false |
116 |
1 |
|
T1 |
1 |
|
T115 |
7 |
|
T374 |
1 |
| true |
5676 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1092 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T23 |
1 |
| others[1] |
1050 |
1 |
|
T5 |
2 |
|
T22 |
1 |
|
T39 |
6 |
| others[2] |
1089 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
| others[3] |
1742 |
1 |
|
T5 |
3 |
|
T18 |
1 |
|
T25 |
1 |
| false |
532 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T38 |
1 |
| true |
1393 |
1 |
|
T15 |
1 |
|
T24 |
1 |
|
T31 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T21 |
1 |
|
T130 |
1 |
|
T131 |
1 |
| others[1] |
202 |
1 |
|
T115 |
7 |
|
T214 |
1 |
|
T382 |
1 |
| others[2] |
265 |
1 |
|
T18 |
1 |
|
T29 |
1 |
|
T136 |
1 |
| others[3] |
398 |
1 |
|
T15 |
1 |
|
T22 |
1 |
|
T31 |
1 |
| false |
132 |
1 |
|
T115 |
4 |
|
T127 |
1 |
|
T67 |
9 |
| true |
5651 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T1 |
1 |
|
T115 |
12 |
|
T214 |
1 |
| others[1] |
207 |
1 |
|
T33 |
1 |
|
T115 |
7 |
|
T316 |
1 |
| others[2] |
239 |
1 |
|
T131 |
1 |
|
T62 |
1 |
|
T115 |
10 |
| others[3] |
378 |
1 |
|
T115 |
16 |
|
T375 |
1 |
|
T304 |
1 |
| false |
120 |
1 |
|
T103 |
1 |
|
T115 |
5 |
|
T382 |
1 |
| true |
5706 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T5 |
3 |
|
T39 |
4 |
|
T40 |
1 |
| others[1] |
1245 |
1 |
|
T3 |
1 |
|
T39 |
9 |
|
T87 |
1 |
| others[2] |
1219 |
1 |
|
T5 |
3 |
|
T25 |
1 |
|
T39 |
12 |
| others[3] |
2118 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
2 |
| false |
639 |
1 |
|
T5 |
1 |
|
T39 |
6 |
|
T103 |
1 |
| true |
443 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T5 |
2 |
|
T39 |
8 |
|
T114 |
1 |
| others[1] |
1301 |
1 |
|
T5 |
3 |
|
T19 |
1 |
|
T38 |
1 |
| others[2] |
1220 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
11 |
| others[3] |
2021 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
2 |
| false |
682 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T39 |
3 |
| true |
424 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T103 |
1 |
|
T115 |
2 |
|
T67 |
2 |
| others[1] |
117 |
1 |
|
T131 |
1 |
|
T115 |
4 |
|
T378 |
1 |
| others[2] |
119 |
1 |
|
T2 |
1 |
|
T115 |
6 |
|
T99 |
1 |
| others[3] |
171 |
1 |
|
T1 |
1 |
|
T103 |
1 |
|
T131 |
1 |
| false |
60 |
1 |
|
T115 |
2 |
|
T374 |
1 |
|
T372 |
1 |
| true |
6338 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T24 |
1 |
|
T103 |
1 |
|
T130 |
1 |
| others[1] |
224 |
1 |
|
T103 |
1 |
|
T115 |
13 |
|
T329 |
1 |
| others[2] |
259 |
1 |
|
T23 |
1 |
|
T31 |
1 |
|
T51 |
1 |
| others[3] |
391 |
1 |
|
T18 |
1 |
|
T42 |
1 |
|
T30 |
1 |
| false |
114 |
1 |
|
T115 |
6 |
|
T375 |
1 |
|
T67 |
4 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1103 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T18 |
1 |
| others[1] |
1114 |
1 |
|
T5 |
2 |
|
T39 |
8 |
|
T63 |
3 |
| others[2] |
1048 |
1 |
|
T5 |
1 |
|
T39 |
12 |
|
T114 |
1 |
| others[3] |
1777 |
1 |
|
T17 |
1 |
|
T5 |
5 |
|
T19 |
1 |
| false |
545 |
1 |
|
T3 |
1 |
|
T23 |
1 |
|
T39 |
3 |
| true |
1311 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T18 |
1 |
|
T31 |
1 |
|
T115 |
10 |
| others[1] |
210 |
1 |
|
T29 |
1 |
|
T115 |
9 |
|
T105 |
1 |
| others[2] |
236 |
1 |
|
T42 |
1 |
|
T103 |
1 |
|
T62 |
1 |
| others[3] |
386 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T103 |
1 |
| false |
115 |
1 |
|
T115 |
3 |
|
T280 |
1 |
|
T67 |
5 |
| true |
5733 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T18 |
1 |
|
T115 |
9 |
|
T67 |
6 |
| others[1] |
231 |
1 |
|
T103 |
1 |
|
T115 |
9 |
|
T316 |
1 |
| others[2] |
237 |
1 |
|
T1 |
1 |
|
T115 |
8 |
|
T372 |
1 |
| others[3] |
368 |
1 |
|
T33 |
1 |
|
T115 |
20 |
|
T375 |
1 |
| false |
113 |
1 |
|
T115 |
4 |
|
T376 |
1 |
|
T212 |
1 |
| true |
5717 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T17 |
1 |
|
T21 |
1 |
|
T39 |
11 |
| others[1] |
1228 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T39 |
10 |
| others[2] |
1269 |
1 |
|
T5 |
2 |
|
T39 |
9 |
|
T167 |
1 |
| others[3] |
2041 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
5 |
| false |
644 |
1 |
|
T5 |
1 |
|
T39 |
3 |
|
T40 |
1 |
| true |
442 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T39 |
6 |
|
T103 |
1 |
|
T63 |
2 |
| others[1] |
1254 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[2] |
1265 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T39 |
5 |
| others[3] |
2012 |
1 |
|
T3 |
1 |
|
T5 |
5 |
|
T38 |
1 |
| false |
668 |
1 |
|
T5 |
1 |
|
T39 |
4 |
|
T63 |
1 |
| true |
433 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
137 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
2 |
| others[1] |
106 |
1 |
|
T115 |
5 |
|
T316 |
1 |
|
T214 |
1 |
| others[2] |
116 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
7 |
| others[3] |
178 |
1 |
|
T115 |
2 |
|
T379 |
1 |
|
T99 |
1 |
| false |
54 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T115 |
1 |
| true |
6307 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T1 |
1 |
|
T42 |
1 |
|
T61 |
1 |
| others[1] |
256 |
1 |
|
T43 |
1 |
|
T34 |
1 |
|
T29 |
1 |
| others[2] |
259 |
1 |
|
T23 |
1 |
|
T131 |
1 |
|
T136 |
1 |
| others[3] |
397 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T24 |
1 |
| false |
131 |
1 |
|
T115 |
6 |
|
T376 |
1 |
|
T372 |
1 |
| true |
5632 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1043 |
1 |
|
T17 |
1 |
|
T5 |
3 |
|
T19 |
1 |
| others[1] |
1032 |
1 |
|
T39 |
5 |
|
T40 |
1 |
|
T33 |
1 |
| others[2] |
1103 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T22 |
1 |
| others[3] |
1792 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T25 |
1 |
| false |
526 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T39 |
4 |
| true |
1402 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T23 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |