Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T51 |
1 |
|
T28 |
1 |
|
T29 |
1 |
| others[1] |
235 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
| others[2] |
249 |
1 |
|
T131 |
1 |
|
T136 |
1 |
|
T115 |
17 |
| others[3] |
392 |
1 |
|
T2 |
1 |
|
T115 |
12 |
|
T214 |
1 |
| false |
131 |
1 |
|
T42 |
1 |
|
T115 |
4 |
|
T373 |
1 |
| true |
5688 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T115 |
6 |
|
T212 |
1 |
|
T67 |
8 |
| others[1] |
236 |
1 |
|
T2 |
1 |
|
T115 |
13 |
|
T105 |
1 |
| others[2] |
232 |
1 |
|
T103 |
1 |
|
T115 |
10 |
|
T374 |
1 |
| others[3] |
373 |
1 |
|
T1 |
1 |
|
T131 |
1 |
|
T115 |
28 |
| false |
106 |
1 |
|
T103 |
1 |
|
T115 |
5 |
|
T372 |
1 |
| true |
5739 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| others[1] |
1222 |
1 |
|
T5 |
1 |
|
T39 |
7 |
|
T63 |
2 |
| others[2] |
1274 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T39 |
7 |
| others[3] |
2066 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| false |
637 |
1 |
|
T39 |
7 |
|
T63 |
1 |
|
T113 |
13 |
| true |
441 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1179 |
1 |
|
T39 |
9 |
|
T63 |
3 |
|
T112 |
1 |
| others[1] |
1285 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
8 |
| others[2] |
1345 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T39 |
12 |
| others[3] |
2039 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
7 |
| false |
627 |
1 |
|
T39 |
3 |
|
T113 |
10 |
|
T85 |
8 |
| true |
423 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T2 |
1 |
|
T115 |
4 |
|
T374 |
1 |
| others[1] |
97 |
1 |
|
T115 |
2 |
|
T212 |
1 |
|
T99 |
1 |
| others[2] |
113 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
2 |
| others[3] |
171 |
1 |
|
T131 |
1 |
|
T115 |
4 |
|
T376 |
1 |
| false |
70 |
1 |
|
T103 |
1 |
|
T115 |
6 |
|
T67 |
1 |
| true |
6342 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T24 |
1 |
|
T42 |
1 |
|
T43 |
1 |
| others[1] |
257 |
1 |
|
T34 |
1 |
|
T115 |
13 |
|
T105 |
1 |
| others[2] |
249 |
1 |
|
T22 |
1 |
|
T61 |
1 |
|
T130 |
1 |
| others[3] |
422 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T103 |
1 |
| false |
102 |
1 |
|
T33 |
1 |
|
T115 |
1 |
|
T280 |
1 |
| true |
5651 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1072 |
1 |
|
T3 |
1 |
|
T5 |
3 |
|
T23 |
1 |
| others[1] |
1063 |
1 |
|
T39 |
7 |
|
T114 |
1 |
|
T63 |
1 |
| others[2] |
1072 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
1788 |
1 |
|
T5 |
4 |
|
T18 |
1 |
|
T21 |
1 |
| false |
565 |
1 |
|
T1 |
1 |
|
T38 |
1 |
|
T39 |
7 |
| true |
1338 |
1 |
|
T22 |
1 |
|
T24 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T130 |
1 |
|
T136 |
1 |
|
T30 |
1 |
| others[1] |
236 |
1 |
|
T42 |
1 |
|
T115 |
11 |
|
T280 |
1 |
| others[2] |
234 |
1 |
|
T29 |
1 |
|
T115 |
4 |
|
T126 |
1 |
| others[3] |
367 |
1 |
|
T18 |
1 |
|
T115 |
22 |
|
T374 |
1 |
| false |
120 |
1 |
|
T115 |
8 |
|
T305 |
1 |
|
T67 |
3 |
| true |
5743 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T131 |
1 |
|
T115 |
11 |
|
T374 |
1 |
| others[1] |
198 |
1 |
|
T115 |
6 |
|
T214 |
1 |
|
T373 |
1 |
| others[2] |
224 |
1 |
|
T115 |
8 |
|
T372 |
1 |
|
T212 |
1 |
| others[3] |
353 |
1 |
|
T18 |
1 |
|
T62 |
1 |
|
T115 |
11 |
| false |
129 |
1 |
|
T115 |
12 |
|
T67 |
6 |
|
T383 |
1 |
| true |
5765 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T17 |
1 |
|
T5 |
3 |
|
T38 |
1 |
| others[1] |
1200 |
1 |
|
T39 |
7 |
|
T167 |
1 |
|
T63 |
1 |
| others[2] |
1302 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T39 |
11 |
| others[3] |
2072 |
1 |
|
T3 |
1 |
|
T5 |
6 |
|
T25 |
1 |
| false |
666 |
1 |
|
T19 |
1 |
|
T24 |
1 |
|
T39 |
7 |
| true |
441 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[1] |
1262 |
1 |
|
T5 |
1 |
|
T39 |
9 |
|
T113 |
16 |
| others[2] |
1245 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T39 |
12 |
| others[3] |
2126 |
1 |
|
T5 |
4 |
|
T19 |
1 |
|
T25 |
1 |
| false |
619 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T39 |
5 |
| true |
420 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
121 |
1 |
|
T131 |
2 |
|
T115 |
2 |
|
T372 |
1 |
| others[1] |
112 |
1 |
|
T103 |
1 |
|
T115 |
6 |
|
T67 |
1 |
| others[2] |
101 |
1 |
|
T115 |
5 |
|
T372 |
1 |
|
T379 |
1 |
| others[3] |
181 |
1 |
|
T2 |
1 |
|
T103 |
1 |
|
T115 |
5 |
| false |
54 |
1 |
|
T115 |
2 |
|
T67 |
4 |
|
T88 |
1 |
| true |
6329 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T33 |
1 |
| others[1] |
240 |
1 |
|
T31 |
1 |
|
T103 |
2 |
|
T115 |
7 |
| others[2] |
218 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T28 |
1 |
| others[3] |
406 |
1 |
|
T61 |
1 |
|
T131 |
1 |
|
T115 |
19 |
| false |
146 |
1 |
|
T30 |
1 |
|
T115 |
3 |
|
T316 |
1 |
| true |
5649 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1043 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
3 |
| others[1] |
1103 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T39 |
9 |
| others[2] |
1094 |
1 |
|
T1 |
1 |
|
T5 |
4 |
|
T39 |
11 |
| others[3] |
1742 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T39 |
9 |
| false |
542 |
1 |
|
T18 |
1 |
|
T23 |
1 |
|
T25 |
1 |
| true |
1374 |
1 |
|
T22 |
1 |
|
T24 |
1 |
|
T31 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T15 |
1 |
|
T115 |
8 |
|
T374 |
1 |
| others[1] |
228 |
1 |
|
T1 |
1 |
|
T115 |
8 |
|
T109 |
1 |
| others[2] |
240 |
1 |
|
T28 |
1 |
|
T131 |
1 |
|
T30 |
1 |
| others[3] |
397 |
1 |
|
T33 |
1 |
|
T103 |
1 |
|
T29 |
1 |
| false |
131 |
1 |
|
T31 |
1 |
|
T115 |
5 |
|
T277 |
1 |
| true |
5661 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T115 |
8 |
|
T67 |
9 |
|
T380 |
1 |
| others[1] |
222 |
1 |
|
T115 |
15 |
|
T316 |
1 |
|
T214 |
1 |
| others[2] |
232 |
1 |
|
T131 |
1 |
|
T115 |
10 |
|
T374 |
1 |
| others[3] |
354 |
1 |
|
T103 |
1 |
|
T115 |
15 |
|
T372 |
2 |
| false |
130 |
1 |
|
T18 |
1 |
|
T62 |
1 |
|
T115 |
4 |
| true |
5739 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[1] |
1247 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T39 |
14 |
| others[2] |
1266 |
1 |
|
T5 |
1 |
|
T39 |
6 |
|
T167 |
1 |
| others[3] |
2079 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
5 |
| false |
642 |
1 |
|
T5 |
1 |
|
T39 |
6 |
|
T40 |
1 |
| true |
439 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T5 |
1 |
|
T39 |
12 |
|
T10 |
1 |
| others[1] |
1284 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| others[2] |
1208 |
1 |
|
T5 |
1 |
|
T39 |
8 |
|
T114 |
1 |
| others[3] |
2090 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
5 |
| false |
647 |
1 |
|
T38 |
1 |
|
T112 |
1 |
|
T113 |
15 |
| true |
418 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T2 |
1 |
|
T115 |
4 |
|
T67 |
4 |
| others[1] |
110 |
1 |
|
T115 |
6 |
|
T378 |
1 |
|
T218 |
1 |
| others[2] |
122 |
1 |
|
T115 |
4 |
|
T374 |
1 |
|
T375 |
1 |
| others[3] |
181 |
1 |
|
T103 |
2 |
|
T131 |
1 |
|
T115 |
6 |
| false |
52 |
1 |
|
T131 |
1 |
|
T115 |
1 |
|
T67 |
1 |
| true |
6324 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T42 |
1 |
|
T136 |
1 |
|
T115 |
10 |
| others[1] |
238 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T115 |
11 |
| others[2] |
266 |
1 |
|
T31 |
1 |
|
T51 |
1 |
|
T34 |
1 |
| others[3] |
360 |
1 |
|
T15 |
1 |
|
T103 |
1 |
|
T130 |
1 |
| false |
129 |
1 |
|
T131 |
1 |
|
T115 |
5 |
|
T337 |
1 |
| true |
5663 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1075 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
3 |
| others[1] |
1024 |
1 |
|
T19 |
1 |
|
T39 |
8 |
|
T42 |
1 |
| others[2] |
1108 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[3] |
1784 |
1 |
|
T3 |
1 |
|
T5 |
3 |
|
T22 |
1 |
| false |
524 |
1 |
|
T5 |
2 |
|
T21 |
1 |
|
T113 |
7 |
| true |
1383 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T31 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T42 |
1 |
|
T28 |
1 |
|
T62 |
1 |
| others[1] |
231 |
1 |
|
T29 |
1 |
|
T115 |
7 |
|
T109 |
1 |
| others[2] |
233 |
1 |
|
T115 |
12 |
|
T329 |
1 |
|
T306 |
1 |
| others[3] |
350 |
1 |
|
T18 |
1 |
|
T33 |
1 |
|
T51 |
1 |
| false |
127 |
1 |
|
T115 |
6 |
|
T214 |
1 |
|
T305 |
1 |
| true |
5712 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T1 |
1 |
|
T115 |
9 |
|
T316 |
1 |
| others[1] |
225 |
1 |
|
T115 |
23 |
|
T372 |
1 |
|
T67 |
9 |
| others[2] |
224 |
1 |
|
T62 |
1 |
|
T115 |
14 |
|
T105 |
1 |
| others[3] |
360 |
1 |
|
T2 |
1 |
|
T115 |
12 |
|
T214 |
1 |
| false |
121 |
1 |
|
T21 |
1 |
|
T115 |
4 |
|
T212 |
1 |
| true |
5724 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
4 |
| others[1] |
1286 |
1 |
|
T39 |
9 |
|
T114 |
1 |
|
T63 |
3 |
| others[2] |
1234 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T25 |
1 |
| others[3] |
2049 |
1 |
|
T15 |
1 |
|
T5 |
3 |
|
T24 |
1 |
| false |
623 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T39 |
3 |
| true |
429 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T5 |
3 |
|
T39 |
8 |
|
T40 |
1 |
| others[1] |
1229 |
1 |
|
T5 |
1 |
|
T25 |
1 |
|
T39 |
4 |
| others[2] |
1238 |
1 |
|
T5 |
1 |
|
T31 |
1 |
|
T39 |
8 |
| others[3] |
2104 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
4 |
| false |
635 |
1 |
|
T3 |
1 |
|
T39 |
1 |
|
T167 |
1 |
| true |
421 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T103 |
1 |
|
T115 |
1 |
|
T374 |
1 |
| others[1] |
120 |
1 |
|
T1 |
1 |
|
T103 |
1 |
|
T115 |
5 |
| others[2] |
112 |
1 |
|
T2 |
1 |
|
T115 |
2 |
|
T372 |
1 |
| others[3] |
192 |
1 |
|
T131 |
2 |
|
T115 |
4 |
|
T214 |
1 |
| false |
57 |
1 |
|
T115 |
5 |
|
T373 |
1 |
|
T384 |
1 |
| true |
6307 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T28 |
1 |
|
T30 |
1 |
|
T115 |
6 |
| others[1] |
231 |
1 |
|
T24 |
1 |
|
T43 |
1 |
|
T61 |
1 |
| others[2] |
265 |
1 |
|
T115 |
11 |
|
T280 |
1 |
|
T372 |
1 |
| others[3] |
399 |
1 |
|
T2 |
1 |
|
T51 |
1 |
|
T131 |
1 |
| false |
116 |
1 |
|
T15 |
1 |
|
T62 |
1 |
|
T115 |
6 |
| true |
5658 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
3 |
| others[1] |
1092 |
1 |
|
T23 |
1 |
|
T39 |
11 |
|
T43 |
1 |
| others[2] |
1042 |
1 |
|
T25 |
1 |
|
T39 |
6 |
|
T10 |
1 |
| others[3] |
1728 |
1 |
|
T5 |
4 |
|
T38 |
1 |
|
T39 |
16 |
| false |
558 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
2 |
| true |
1417 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T18 |
1 |
|
T131 |
1 |
|
T115 |
9 |
| others[1] |
245 |
1 |
|
T130 |
1 |
|
T115 |
13 |
|
T372 |
1 |
| others[2] |
229 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T115 |
12 |
| others[3] |
383 |
1 |
|
T22 |
1 |
|
T42 |
1 |
|
T51 |
1 |
| false |
115 |
1 |
|
T21 |
1 |
|
T103 |
1 |
|
T115 |
5 |
| true |
5678 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T62 |
1 |
|
T115 |
8 |
|
T382 |
1 |
| others[1] |
230 |
1 |
|
T1 |
1 |
|
T115 |
23 |
|
T67 |
7 |
| others[2] |
249 |
1 |
|
T115 |
8 |
|
T372 |
1 |
|
T67 |
13 |
| others[3] |
359 |
1 |
|
T33 |
1 |
|
T115 |
17 |
|
T372 |
1 |
| false |
108 |
1 |
|
T103 |
1 |
|
T115 |
2 |
|
T304 |
1 |
| true |
5707 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T5 |
4 |
|
T38 |
1 |
|
T39 |
7 |
| others[1] |
1208 |
1 |
|
T31 |
1 |
|
T39 |
10 |
|
T103 |
1 |
| others[2] |
1241 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| others[3] |
2102 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T5 |
3 |
| false |
633 |
1 |
|
T39 |
4 |
|
T63 |
1 |
|
T113 |
9 |
| true |
440 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |