Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T39 |
6 |
|
T103 |
1 |
|
T63 |
1 |
| others[1] |
1222 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T19 |
1 |
| others[2] |
1301 |
1 |
|
T5 |
2 |
|
T39 |
8 |
|
T103 |
1 |
| others[3] |
2050 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
4 |
| false |
670 |
1 |
|
T39 |
7 |
|
T167 |
1 |
|
T63 |
1 |
| true |
425 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T115 |
1 |
|
T67 |
5 |
|
T386 |
1 |
| others[1] |
114 |
1 |
|
T103 |
1 |
|
T115 |
7 |
|
T99 |
2 |
| others[2] |
124 |
1 |
|
T103 |
1 |
|
T131 |
2 |
|
T115 |
9 |
| others[3] |
204 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T115 |
6 |
| false |
60 |
1 |
|
T115 |
2 |
|
T372 |
1 |
|
T67 |
3 |
| true |
6304 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T136 |
1 |
|
T115 |
8 |
|
T67 |
7 |
| others[1] |
233 |
1 |
|
T31 |
1 |
|
T103 |
1 |
|
T115 |
9 |
| others[2] |
241 |
1 |
|
T42 |
1 |
|
T61 |
1 |
|
T30 |
1 |
| others[3] |
404 |
1 |
|
T23 |
1 |
|
T24 |
1 |
|
T33 |
1 |
| false |
123 |
1 |
|
T22 |
1 |
|
T115 |
5 |
|
T372 |
1 |
| true |
5671 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1100 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T25 |
1 |
| others[1] |
1067 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| others[2] |
1101 |
1 |
|
T5 |
2 |
|
T39 |
5 |
|
T43 |
1 |
| others[3] |
1759 |
1 |
|
T5 |
6 |
|
T38 |
1 |
|
T39 |
17 |
| false |
501 |
1 |
|
T2 |
1 |
|
T39 |
4 |
|
T32 |
1 |
| true |
1370 |
1 |
|
T15 |
1 |
|
T22 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T62 |
1 |
|
T115 |
7 |
|
T280 |
1 |
| others[1] |
260 |
1 |
|
T33 |
1 |
|
T28 |
1 |
|
T115 |
15 |
| others[2] |
220 |
1 |
|
T1 |
1 |
|
T131 |
1 |
|
T115 |
9 |
| others[3] |
384 |
1 |
|
T31 |
1 |
|
T21 |
1 |
|
T42 |
1 |
| false |
120 |
1 |
|
T51 |
1 |
|
T115 |
3 |
|
T35 |
1 |
| true |
5686 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T18 |
1 |
|
T115 |
11 |
|
T375 |
1 |
| others[1] |
217 |
1 |
|
T1 |
1 |
|
T115 |
7 |
|
T109 |
1 |
| others[2] |
211 |
1 |
|
T115 |
11 |
|
T218 |
1 |
|
T382 |
1 |
| others[3] |
355 |
1 |
|
T2 |
1 |
|
T103 |
1 |
|
T115 |
11 |
| false |
112 |
1 |
|
T115 |
3 |
|
T303 |
1 |
|
T67 |
7 |
| true |
5786 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T5 |
4 |
|
T39 |
8 |
|
T113 |
11 |
| others[1] |
1272 |
1 |
|
T5 |
1 |
|
T39 |
7 |
|
T103 |
1 |
| others[2] |
1285 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T38 |
1 |
| others[3] |
2030 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| false |
662 |
1 |
|
T5 |
1 |
|
T39 |
4 |
|
T63 |
2 |
| true |
430 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T18 |
1 |
| others[1] |
1236 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| others[2] |
1277 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T39 |
6 |
| others[3] |
2052 |
1 |
|
T5 |
4 |
|
T38 |
1 |
|
T25 |
1 |
| false |
646 |
1 |
|
T39 |
2 |
|
T63 |
2 |
|
T113 |
6 |
| true |
427 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
4 |
| others[1] |
112 |
1 |
|
T115 |
3 |
|
T372 |
1 |
|
T99 |
1 |
| others[2] |
99 |
1 |
|
T33 |
1 |
|
T115 |
2 |
|
T378 |
1 |
| others[3] |
182 |
1 |
|
T2 |
1 |
|
T115 |
4 |
|
T374 |
1 |
| false |
41 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T212 |
1 |
| true |
6354 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T103 |
1 |
|
T130 |
1 |
|
T115 |
7 |
| others[1] |
207 |
1 |
|
T1 |
1 |
|
T42 |
1 |
|
T61 |
1 |
| others[2] |
250 |
1 |
|
T24 |
1 |
|
T31 |
1 |
|
T21 |
1 |
| others[3] |
392 |
1 |
|
T23 |
1 |
|
T34 |
1 |
|
T115 |
21 |
| false |
135 |
1 |
|
T22 |
1 |
|
T115 |
3 |
|
T127 |
1 |
| true |
5677 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T5 |
1 |
|
T39 |
12 |
|
T114 |
1 |
| others[1] |
1071 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T39 |
14 |
| others[2] |
1094 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| others[3] |
1760 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
| false |
525 |
1 |
|
T5 |
1 |
|
T25 |
1 |
|
T39 |
5 |
| true |
1397 |
1 |
|
T18 |
1 |
|
T23 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T51 |
1 |
|
T29 |
1 |
|
T115 |
8 |
| others[1] |
247 |
1 |
|
T103 |
1 |
|
T30 |
1 |
|
T115 |
9 |
| others[2] |
254 |
1 |
|
T18 |
1 |
|
T21 |
1 |
|
T136 |
1 |
| others[3] |
382 |
1 |
|
T1 |
1 |
|
T62 |
1 |
|
T115 |
17 |
| false |
123 |
1 |
|
T2 |
1 |
|
T115 |
5 |
|
T67 |
5 |
| true |
5649 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T62 |
1 |
|
T115 |
10 |
|
T218 |
1 |
| others[1] |
222 |
1 |
|
T115 |
7 |
|
T214 |
1 |
|
T372 |
1 |
| others[2] |
215 |
1 |
|
T115 |
9 |
|
T99 |
1 |
|
T67 |
7 |
| others[3] |
369 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T115 |
15 |
| false |
120 |
1 |
|
T115 |
6 |
|
T67 |
4 |
|
T233 |
1 |
| true |
5763 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1210 |
1 |
|
T17 |
1 |
|
T39 |
7 |
|
T103 |
1 |
| others[1] |
1259 |
1 |
|
T5 |
4 |
|
T19 |
1 |
|
T38 |
1 |
| others[2] |
1301 |
1 |
|
T5 |
1 |
|
T31 |
1 |
|
T39 |
8 |
| others[3] |
2037 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T25 |
1 |
| false |
662 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
8 |
| true |
429 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T5 |
2 |
|
T31 |
1 |
|
T39 |
10 |
| others[1] |
1277 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T39 |
8 |
| others[2] |
1249 |
1 |
|
T39 |
4 |
|
T11 |
1 |
|
T114 |
1 |
| others[3] |
2046 |
1 |
|
T5 |
5 |
|
T19 |
1 |
|
T38 |
1 |
| false |
627 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T39 |
4 |
| true |
422 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T33 |
1 |
|
T115 |
2 |
|
T67 |
4 |
| others[1] |
116 |
1 |
|
T2 |
1 |
|
T103 |
1 |
|
T131 |
1 |
| others[2] |
118 |
1 |
|
T115 |
9 |
|
T372 |
1 |
|
T382 |
1 |
| others[3] |
161 |
1 |
|
T103 |
1 |
|
T131 |
1 |
|
T115 |
1 |
| false |
60 |
1 |
|
T115 |
5 |
|
T99 |
1 |
|
T67 |
3 |
| true |
6323 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T115 |
9 |
|
T35 |
1 |
|
T372 |
1 |
| others[1] |
212 |
1 |
|
T23 |
1 |
|
T33 |
1 |
|
T51 |
1 |
| others[2] |
217 |
1 |
|
T18 |
1 |
|
T61 |
1 |
|
T103 |
1 |
| others[3] |
413 |
1 |
|
T31 |
1 |
|
T21 |
1 |
|
T29 |
1 |
| false |
150 |
1 |
|
T22 |
1 |
|
T131 |
1 |
|
T115 |
11 |
| true |
5654 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T18 |
1 |
| others[1] |
1019 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T38 |
1 |
| others[2] |
1057 |
1 |
|
T15 |
1 |
|
T21 |
1 |
|
T39 |
5 |
| others[3] |
1769 |
1 |
|
T3 |
1 |
|
T5 |
4 |
|
T39 |
13 |
| false |
573 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T39 |
2 |
| true |
1417 |
1 |
|
T1 |
1 |
|
T22 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T115 |
12 |
|
T375 |
1 |
|
T372 |
1 |
| others[1] |
239 |
1 |
|
T62 |
1 |
|
T115 |
14 |
|
T306 |
1 |
| others[2] |
210 |
1 |
|
T115 |
5 |
|
T329 |
1 |
|
T304 |
1 |
| others[3] |
388 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T33 |
1 |
| false |
133 |
1 |
|
T115 |
5 |
|
T374 |
1 |
|
T214 |
1 |
| true |
5688 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T1 |
1 |
|
T62 |
1 |
|
T115 |
7 |
| others[1] |
224 |
1 |
|
T115 |
10 |
|
T374 |
1 |
|
T316 |
1 |
| others[2] |
236 |
1 |
|
T115 |
13 |
|
T378 |
1 |
|
T99 |
1 |
| others[3] |
366 |
1 |
|
T2 |
1 |
|
T115 |
8 |
|
T214 |
1 |
| false |
100 |
1 |
|
T115 |
4 |
|
T304 |
1 |
|
T67 |
2 |
| true |
5773 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T5 |
2 |
|
T39 |
10 |
|
T63 |
1 |
| others[1] |
1184 |
1 |
|
T5 |
1 |
|
T39 |
9 |
|
T40 |
1 |
| others[2] |
1240 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T25 |
1 |
| others[3] |
2120 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
2 |
| false |
648 |
1 |
|
T5 |
2 |
|
T39 |
3 |
|
T87 |
1 |
| true |
435 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T39 |
6 |
| others[1] |
1243 |
1 |
|
T5 |
1 |
|
T39 |
13 |
|
T63 |
2 |
| others[2] |
1237 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T38 |
1 |
| others[3] |
2080 |
1 |
|
T5 |
4 |
|
T19 |
1 |
|
T25 |
1 |
| false |
639 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T24 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
125 |
1 |
|
T131 |
1 |
|
T115 |
5 |
|
T67 |
9 |
| others[1] |
114 |
1 |
|
T33 |
1 |
|
T131 |
1 |
|
T115 |
3 |
| others[2] |
105 |
1 |
|
T115 |
8 |
|
T67 |
2 |
|
T88 |
4 |
| others[3] |
174 |
1 |
|
T2 |
1 |
|
T103 |
1 |
|
T115 |
9 |
| false |
49 |
1 |
|
T103 |
1 |
|
T99 |
1 |
|
T67 |
1 |
| true |
6331 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
257 |
1 |
|
T103 |
1 |
|
T115 |
7 |
|
T116 |
1 |
| others[1] |
253 |
1 |
|
T28 |
1 |
|
T62 |
1 |
|
T115 |
9 |
| others[2] |
235 |
1 |
|
T29 |
1 |
|
T115 |
15 |
|
T375 |
1 |
| others[3] |
404 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
| false |
133 |
1 |
|
T30 |
1 |
|
T115 |
2 |
|
T35 |
1 |
| true |
5616 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T23 |
1 |
|
T39 |
7 |
|
T40 |
1 |
| others[1] |
1065 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[2] |
1114 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T19 |
1 |
| others[3] |
1776 |
1 |
|
T15 |
1 |
|
T5 |
5 |
|
T38 |
1 |
| false |
540 |
1 |
|
T5 |
1 |
|
T25 |
1 |
|
T114 |
1 |
| true |
1351 |
1 |
|
T18 |
1 |
|
T24 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
261 |
1 |
|
T28 |
1 |
|
T115 |
9 |
|
T216 |
1 |
| others[1] |
226 |
1 |
|
T21 |
1 |
|
T130 |
1 |
|
T115 |
6 |
| others[2] |
211 |
1 |
|
T22 |
1 |
|
T136 |
1 |
|
T115 |
9 |
| others[3] |
389 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T131 |
1 |
| false |
102 |
1 |
|
T2 |
1 |
|
T115 |
5 |
|
T67 |
5 |
| true |
5709 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T115 |
10 |
|
T374 |
1 |
|
T378 |
1 |
| others[1] |
239 |
1 |
|
T1 |
1 |
|
T131 |
2 |
|
T115 |
8 |
| others[2] |
210 |
1 |
|
T33 |
1 |
|
T62 |
1 |
|
T115 |
7 |
| others[3] |
367 |
1 |
|
T103 |
1 |
|
T115 |
16 |
|
T316 |
1 |
| false |
110 |
1 |
|
T115 |
4 |
|
T67 |
3 |
|
T88 |
8 |
| true |
5754 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T5 |
1 |
|
T39 |
6 |
|
T10 |
1 |
| others[1] |
1306 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[2] |
1246 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[3] |
2017 |
1 |
|
T3 |
1 |
|
T5 |
5 |
|
T25 |
1 |
| false |
640 |
1 |
|
T5 |
1 |
|
T39 |
3 |
|
T103 |
1 |
| true |
429 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T74 |
1 |
|
T149 |
1 |
|
T229 |
1 |
| others[1] |
4 |
1 |
|
T138 |
1 |
|
T147 |
1 |
|
T387 |
1 |
| others[2] |
12 |
1 |
|
T69 |
1 |
|
T80 |
1 |
|
T148 |
1 |
| others[3] |
5 |
1 |
|
T12 |
1 |
|
T81 |
1 |
|
T157 |
1 |
| false |
6 |
1 |
|
T388 |
1 |
|
T389 |
1 |
|
T390 |
1 |
| true |
48 |
1 |
|
T12 |
1 |
|
T73 |
1 |
|
T74 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T227 |
1 |
|
T391 |
1 |
|
- |
- |
| others[1] |
2 |
1 |
|
T135 |
1 |
|
T392 |
1 |
|
- |
- |
| others[2] |
1 |
1 |
|
T393 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
2 |
1 |
|
T394 |
1 |
|
T395 |
1 |
|
- |
- |
| false |
10 |
1 |
|
T4 |
1 |
|
T258 |
1 |
|
T396 |
1 |
| true |
31 |
1 |
|
T20 |
1 |
|
T27 |
1 |
|
T111 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T397 |
1 |
|
T398 |
1 |
|
- |
- |
| others[1] |
5 |
1 |
|
T111 |
1 |
|
T399 |
1 |
|
T400 |
1 |
| others[2] |
2 |
1 |
|
T401 |
1 |
|
T394 |
1 |
|
- |
- |
| others[3] |
4 |
1 |
|
T27 |
1 |
|
T402 |
1 |
|
T403 |
1 |
| false |
10 |
1 |
|
T20 |
1 |
|
T101 |
1 |
|
T404 |
1 |
| true |
25 |
1 |
|
T4 |
1 |
|
T258 |
1 |
|
T135 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |